An AES/EBU Re-Clocker
Circuit
AES/EBU or
S/PDIF bitstreams often include excessive jitter. In order to remove the
jitter, a type of re- clocking scheme can be executed using an S/PDIF receiver
and transmitter. This circuit can be realized with the AK4114 digital interface
receiver and AK4103A digital interface transmitter. No microcontroller or
software development is required, since both devices can operate in the parallel
(hardware) control mode by pin-strapping.
The AK4103A can be configured in
audio routing mode (transparent mode) by setting the ANS pin = TRANS pin = 1.
In this mode, the channel status (C), user data (U) and validity (V) bits pass
through unaltered. The Block Start (B) signal is configured as an input,
allowing the transmit block structure to be slaved to the block structure of
the receiver. The C, U and V bits are now transmitted with the current audio
sample. In this mode, no CRCC bytes are generated and C bits pass through
unaltered.
The AK4114 receiver has interrupt
pins that generate flags for five different events: unlock, parity error,
PCM/non-PCM data input detect, DTS input detect, and audio / non-audio data
input detect.
