AK4753EN

24-Bit 2ch ADC & 4ch DAC with Limiter and 5band Eq

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Description

The AK4753 is a two input, four output audio CODEC with integrated digital signal processing. The outputs can be configured either as single-ended or differential. An internal PLL allows the chip to run in master clock free mode. The digital signal processing block includes an ALC/limiter, 5 configurable biquads for EQ, volume control, and 4th-order filters for each output channel to enable a variety of configurations. Wide dynamic range is achieved with 96dB SNR for the ADC, and 103dB SNR for the DAC’s. A two-input 8-bit SAR ADC is integrated for processing of external potentiometers, supporting volume and bass control functions. A small external EEP-ROM is used to store the coefficient values for the DSP blocks. The AK4753 is controlled by an I2C control interface.

Key Features

1. Applications: Active Speakers, Potable Docking Stations

2. Digital audio input interface

· Data format: MSB-first, two’s complement

· 16, 20, or 24-bits, I2S, MSB justified, LSB justified, or DSP mode

· Audio sampling rates: 8kHz to 48kHz

3. Analog audio input

· Single-ended input stereo audio ADC

· SNR: 96dB  THD+N: 85dB

· Digital high-pass filter for DC-offset correction

4. Analog audio output

· Four-channel 24-bit audio DAC

· Single-ended or differential output

· SNR: 103dB  THD+N: 88dB

5. 8-bit SAR ADC with two input selector

6. Digital mixer for balancing inputs

7. Digital signal processing block: DSP1, DSP2 independently

· Configurable ALC / limiter function

· Volume control: 0dB to -127dB, 0.5dB steps, mute

· Pre-gain setting: 0dB, +6dB, +12dB, +18dB

· Post-gain setting: 0dB, +3.5dB, +6dB, +8dB

· Five programmable biquads for EQ

· 4th-order high-pass filter or low-pass filter

8. Integrated PLL for master clock-free operation

9. PLL

· Input frequency: 24.576MHz, 24MHz, 22.5792MHz, 12.288MHz, 12MHz, and 11.2896MHz (XTI/MCKI pin)

· 1fs (LRCK pin)

· 32fs or 64fs (BICK pin)

· Input level: CMOS or AC-coupled (XTI/MCKI pin)

10. Master clock input: 256fs, 512fs, 1024fs

11. μP I/F: I2C bus-slave (400kHz Fast-mode)

12. EEP-ROM control I/F: I2C bus-master (400kHz Fast-mode)

13. Ta = -30 ~ +85°C

14. Power supply:

Analog (AVDD): 3.0 ~ 3.6V (typ 3.3V)

Digital (DVDD: 3.0 ~ 3.6V (typ 3.3V)

15 Package: 32 pin QFN (4 x 4 mm, 0.4mm pitch)

14. Evaluation Board: AKD4753


 

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Block Diagram

Block Diagram

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