AK8462

6 channel AFE with 10bit 40MSPS/ch ADC and TG for Linear CCD

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Description

The AK8462 is 40MSPS/ch Analogue Front End IC for Linear CCD sensor, which integrates six channels of correlated double sampling (CDS), 12-bit analog-to-digital converter, on-chip Offset Adjust DAC, PGA, V-by-One HS if and Timing Genrater for CCD control.

 

Key Features

・Maximum conversion rate : 40MSPS / ch.

・Input range : 1.27Vpp(typ.) @ CDS mode

・Input polarity : Negative polarity @CDS mode, Positive or Differential @DC direct mode

・6ch. sampling : CDS circuit (Correlated Double Sampling)

・Offset DAC : Digital black loop compensation circuit built-inSensor offset compensation range = ±150 mV

・PGA : Gain range: 0dB~18dB @ analog 1.5dB step ,

   0~5dB @digital 0.039dB/step (7bit), separate 6 channel

・Built-in auto-gain-control circuit

・Linearity : DNL = −1LSB(min.), +1LSB(max.) Monotone guarantee(10bit)

・V-by-One HS interface output : 1 Lane

・Clock Generator 10MHz ~ 20MHz (0.1MHz step), 20MHz ~ 40MHz (0.2MHz step programmable)

・Timing Generator: CCD control clock

 TG output pins TG0-17

 Shift pulses 10sets (SH0-9)

 Transfer pulses 3sets (P0, P1, P2)

 Pixel rate pulses 2 sets (PRS, PCL)

 Other pulses 1 set (PWM)

 Time resolution Pixel rate ×1/56

 Internal timing pulses SHD, SHR, ADCK, OBP

 Time resolution P0~3, PRS, PCL: pixel cycle x1/56, SH0~9, PWM: pixel cycle

 Generate sensor drive pulse (SHD, SHR, ADCK, OBP) Each ch. same setup.

・SSCG function Internal SSCG function

   Accept frequency diffusion clock.

・4 line serial interface

・Power supplies : AVDD,PVDD,DVDD,QVDD,CVDD,DRVDD: 1.7~.2.0V

        AVDD33,IOVDD,XVDD,TVDD: 3.0~3.6V

・Operation Temperature: 0°C~70°C

・Power consumption : 830mW (typ.)@6ch.mode, 40MSPS / channel

・Package: 72 pin QFN with exposed thermal pad, pin pitch 0.5mm

 

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Block Diagram

Block Diagram

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