AK9256ANK

Dual 14-bit 0.6MSPS ZDS-NS A/D Converter

  • Inquiry

Description

The AK9256ANK is 14-bit 0.6 MSPS ZDS-NS A/D converter(※)
This product is ZDS A/D converters with noise suppression function and capable of improving the system accuracy.
The AK9256ANK is available in a small package, saving space on the printing board.
In addition, 16-bit option, AK9255ANK and different output interface options, the AK9255NK and the AK9256NK, are also available.


AK9255NK

ZDS-NS ADC AK9255NK



(※) ZDS-NS : Zero latency Delta Sigma with Noise Suppression

A ZDS-NS A/D converter realizes ultrafast response of SAR while maintaining high accuracy conversion like a delta-sigma converter, based on AKM’s accumulated experience and know-how in analog-digital LSI technology. A ZDS-NS A/D converter has smaller input capacitance than SARs, reducing the buffer load of the input stage of the IC. Furthermore, the oversampling process is executed inside of the IC, and the averaging process is carried out with a built-in digital filter. Therefore, analog input signal noise can be suppressed, contributing to improving noise characteristics of the system. It also contributes to high-speed processing of a system that needs a noise averaging.

Key Features

AK9256ANK|2ch 14-bit 0.6 MSPS ZDS-NS A/D Converter
Produce Name AK9255NK AK9255ANK AK9256NK AK9256ANK
Number of Channel 2 ch (Simultaneous Sampling)
Resolution 16-bit 14-bit
Sampling Rate 1.0 MSPS 0.5 MSPS 1.1 MSPS 0.6 MSPS
Output Interface 1 Latency 0 Latency 1 Latency 0 Latency
DNL (typ.) -0.8 ~ +0.8 LSB -0.5 ~ +0.5 LSB
INL (typ.) -3.0 ~ +3.0 LSB -1.0 ~ +1.0 LSB
S/(N+D) (typ.) NS Setting 1 84 dBFS 80 dBFS
NS Setting 4 88 dBFS 84 dBFS
S/N (typ.) NS Setting 1 86 dBFS 82 dBFS
NS Setting 4 90 dBFS 85 dBFS
THD (typ.) NS Setting 1 -90 dB -87 dB
NS Setting 4 -94 dB -93 dB
Power Supply VDD: 3.0 ~ 3.6 V
DRVDD: 3.0 ~ 3.6 V
Current Consumption (typ.) 26 mA
Operational Temperature Range -40 ~ 105 °C
Package 16-pin QFN 3 × 3 mm
(pin pitch 0.5 mm)
Schedule Sample Available CY2018/Q1
Mass Product CY2018/Q2

>> Read more

Block Diagram

Block Diagram

Page Top

top