Audio A/D Converters

AKM’s audio A/D converters (ADCs) realizes high quality sound audio systems with original analog-digital mixed technology that delivers high integration and designing flexibility. They are suitable for wide range of audio products such as portable devices, high-end equipments and car entertainment systems.

The History of AKM's A/D Converters
The History of AKM's A/D Converters

The History of AKM's A/D Converters Since 1987

AKM released a first generation delta-sigma A/D converter, (ADC), in 1987, and a world class fifth-order delta-sigma A/D converter in 1992.  AKM's quality ADC had piqued attention in the audio industry. "2-2 cascade connection", technology that maximized the ADC performance was introduced in 1996. Since then, AKM has been providing ADCs with world class performance by developing advanced technologies such as low power consumption, multi-bit, and AKM's original bi-directional DWA (Data Weighted Average) technology.  In addition, AKM has been improving the conversion resolution from the first generation of 16-bit to 18, to 24, and now 32-bit, and expanding the sampling frequency from 48kHz up to 768kHz, as a worldwide cutting edge leader of audio capture technology.
A new generation architecture, the "VELVET SOUND", brand launched in 2014.  As the first product of VELVET SOUND, the flagship VERITA AK5397 with world leading performance of 127dB S/N was released. In 2016, four multi-channel products were added to each premium high-end ADC, the AK557X series and the premium ADC AK555X series.  In total, nine products are available in the 32-bit premium ADC lineup.
AKM products have been widely adopted by well-established companies from high-end to consumer uses around the world due to the advanced solutions AKM provides with many years’ experience.

Pickup

AK5701: Low power 2ch ADC with ALC, MIC-Amp and PLL

The AK5701 is a low voltage 16-bit A/D converter for portable audio systems. Input circuits include a Microphone-Amplifier and an ALC (Auto Level Control) circuit that is suitable for portable application with recording function. In addition, PLL is integrated, therefore it is easy to connect with DSP. The AK5701 is available in a 24pin QFN package, utilizing less board space than competitive offerings.

Stereo ADCs

Part# Data
Sheet
Automotive
Qualified
Ch# Analog I Bits Max fs THD+N S/N Vdd PLL MIC
Amp
Others





Bits kHz

V      
   
AK5355VNYes2Single1650-85912.1 to 3.6Yes
AK5355VTYes2Single1650-85912.1 to 3.6Yes
AK5357ET2Single2496-881022.7 to 5.5
AK5357VTYes2Single2496-881022.7 to 5.5
AK5359VTYes2Single24216-941025.0
AK5365VQ2Single2496-941035.0Pre-Amp, ALC
AK5367AEF2Single2496-901025.0 and 3.3Capless Input, Pre-Amp
AK5381VTYes2Single2496-961065.0
AK5386VTYes2Single24216-961105.0
AK5397EQ2Diff32768-108127(130*)5.0/3.3VELVETSOUND
AK5552VN
Yes2Diff32768-106115(118*)5.0VELVETSOUND
AK5572EN2Diff32768-112121(124*)5.0VELVETSOUND
AK5701KNYes2Single1648-78892.4 to 3.6YesYesALC
AK5701VN2Single1648-78892.4 to 3.6YesYesALC
AK5720VTYes2Single2496-941022.7 to 5.5YesCascade TDM I/F, Short Group Delay

Multi-channel ADCs

Part# Data
Sheet
Automotive
Qualified
Ch# Analog I Bits Max fs THD+N S/N Vdd PLL MIC
Amp
Others





Bits kHz

V      
   
AK5388AEQ4Diff24216-1101205.0/3.3Cascade TDM I/F, Short Group Delay
AK5534VN
Yes4Diff32768-103111(117*)

3.0 to 3.6

VELVETSOUND
AK5536VN
Yes6Diff32768-103111(118*)

3.0 to 3.6

VELVETSOUND
AK5538VN
Yes8Diff32768-103111(120*)

3.0 to 3.6

VELVETSOUND
AK5554VN
Yes4Diff32768-106115(121*)

5.0

VELVETSOUND
AK5556VN
Yes6Diff32768-106115(122*)5.0VELVETSOUND
AK5558VN
Yes8Diff32768-106115(124*)5.0VELVETSOUND
AK5574EN4Diff32768-112121(127*)5.0VELVETSOUND
AK5576EN6Diff32768-112121(128*)5.0VELVETSOUND
AK5578EN8Diff32768-112121(130*)5.0VELVETSOUND
AK5702VN4Single1648-83892.4 to 3.6YesYesALC, Cascade TDM I/F
AK5703EN4Single / Diff2448-85962.4 to 3.6YesYesALC, Cascade TDM I/F
AK5730VQYes4Diff2448-931003.0 to 3.6YesMic-diagnostics, Cascade TDM I/F

Microphone ADCs

Part# Data
Sheet
Automotive
Qualified
Ch# Analog I Bits Max fs THD+N S/N Vdd PLL MIC
Amp
Others
Bits kHz V
   
AK5355VNYes2Single1650-85912.1 to 3.6Yes
AK5355VTYes2Single1650-85912.1 to 3.6Yes
AK5701KNYes2Single1648-78892.4 to 3.6YesYesALC
AK5701VN2Single1648-78892.4 to 3.6YesYesALC
AK5702VN4Single1648-83892.4 to 3.6YesYesALC, Cascade TDM I/F
AK5703EN4Single / Diff2448-85962.4 to 3.6YesYesALC, Cascade TDM I/F
AK5720VTYes2Single2496-941022.7 to 5.5YesCascade TDM I/F, Short Group Delay
AK5730VQYes4Diff2448-931003.0 to 3.6YesMic-diagnostics, Cascade TDM I/F

Low Power ADCs

Part# Data
Sheet
Automotive
Qualified
Ch# Analog I Bits Max fs THD+N S/N Vdd PLL MIC
Amp
Others





Bits kHz

V      
   
AK5355VNYes2Single1650-85912.1 to 3.6Yes
AK5355VTYes2Single1650-85912.1 to 3.6Yes
AK5357ET2Single2496-881022.7 to 5.5
AK5357VTYes2Single2496-881022.7 to 5.5
AK5373EQ
2Diff2448-85913.0 to 3.6YesYes
AK5374EN2Diff2448-85913.0 to 3.6YesYes
AK5701KNYes2Single1648-78892.4 to 3.6YesYesALC
AK5701VN2Single1648-78892.4 to 3.6YesYesALC
AK5702VN4Single1648-83892.4 to 3.6YesYesALC, Cascade TDM I/F
AK5703EN4Single / Diff2448-85962.4 to 3.6YesYesALC, Cascade TDM I/F
AK5720VTYes2Single2496-941022.7 to 5.5YesCascade TDM I/F, Short Group Delay
AK5730VQYes4Diff2448-931003.0 to 3.6YesMic-diagnostics, Cascade TDM I/F

USB ADCs

Part# Data
Sheet
Automotive
Qualified
Ch# Analog I Bits Max fs THD+N S/N Vdd PLL MIC
Amp
Others





Bits kHz

V      
   
AK5373EQ
2Diff2448-85913.0 to 3.6YesYes
AK5374EN2Diff2448-85913.0 to 3.6YesYes

[Notes]
* RND: Recommend for New Design
* NRND: Not Recommend for New Design

AKM Automotive Products
AdvancedAudioDevices VELVET SOUND

NEW AK5534VN AK5536VN AK5538VN
111dB 768kHz/32-bit 4/6/8ch Advanced Audio ADC

AK5538VN

The AK553x capture incredible detailed and the true sound expression with its high resolution 32-bit processing by AKMs proprietary VELVET SOUND architecture that has been widely adopted by well-established high-end audio companies. This high resolution processing and noise tolerance designs of the AK553x realize a low distortion recording. Digital output supports unsurpassed high resolution sound, up to 768 kHz sampling rate and 11.2 MHz DSD output is available.

Automotive ADCs

Part# Data
Sheet
Automotive
Qualified
Ch# Analog I Bits Max fs THD+N S/N Vdd PLL MIC
Amp
Others





Bits kHz

V      
   
AK5355VNYes2Single1650-85912.1 to 3.6Yes
AK5355VTYes2Single1650-85912.1 to 3.6Yes
AK5357VTYes2Single2496-881022.7 to 5.5
AK5359VTYes2Single24216-941025.0
AK5381VTYes2Single2496-961065.0
AK5386VTYes2Single24216-961105.0
AK5534VN
Yes4Diff32768-103111(117*)

3.0 to 3.6

VELVETSOUND
AK5536VN
Yes6Diff32768-103111(118*)

3.0 to 3.6

VELVETSOUND
AK5538VN
Yes8Diff32768-103111(120*)

3.0 to 3.6

VELVETSOUND
AK5552VN
Yes2Diff32768-106115(118*)5.0VELVETSOUND
AK5554VN
Yes4Diff32768-106115(121*)

5.0

VELVETSOUND
AK5556VN
Yes6Diff32768-106115(122*)5.0VELVETSOUND
AK5558VN
Yes8Diff32768-106115(124*)5.0VELVETSOUND
AK5701KNYes2Single1648-78892.4 to 3.6YesYesALC
AK5720VTYes2Single2496-941022.7 to 5.5YesCascade TDM I/F, Short Group Delay
AK5730VQYes4Diff2448-931003.0 to 3.6YesMic-diagnostics, Cascade TDM I/F

[Notes]
* RND: Recommend for New Design
* NRND: Not Recommend for New Design

FAQs
(Frequently Asked Questions)

Audio A/D Converters
Questions & Answers

Questions

[Q1001] What are the clock input pin and the data output pin statuses in power-down mode?

[A1001] The clock input pins are in Hi-z status. The data output pins are in Low level.

[Q1002] Is there any restriction about PDN rising time?

[A1002] There is no restriction about PDN rising time.

[Q1003] Which action does execute power-down release: PDN pin level (H/L) detection or clcok edge input?

[A1003] Power-down is released by MCLK and LRCK edges after the PDN pin is set to "H."

[Q1004] What is the power-down sequence?

[A1004] Stopping the clocks after setting the PDN pin = "H" → "L" is preferred. However, if the audio clocks are stopped first the device will enter power-down mode automatically for almost all recent generation devices. Please refer to the datasheet of each device in detail.

[Q1005] Is there any problem if the PDN pin is kept to "L" when power supplies are On and then it is set to "H"?
In the datasheet, it could be understood as that the PDN pin should be set to "L" first and set to "H" (H→L→H) after power supplies are on.

[A1005] No Problem. Turn power supplies on while the PDN pin = "L" and then set the PDN pin to "H" after Reset period (tPD) is passed.

[Q1006] When is the appropriate timing to input external clocks?

[A1006] If the power supplies are On, external clocks can be input at any timing regardless of power-down release.

[Q1007] Do I have to care about the input order of clocks?

[A1007] There is no restriction about the input order of clocks.

[Q1008] What does the expression "The LRCK clock input must be synchronized with MCLK, however the phase is not critical." in the datasheet mean substantially?

[A1008] MCLK and LRCK should be generated by dividing the same clock source. The phase difference will not matter in this case.

[Q1009] Is there any restriction about the rise/fall time of external input clock?

[A1009] There is no timing restriction about the external clock input. However, the input clock swing must transit monotonically without including higher frequency noise.

[Q1010] Does clock jitter on LRCK or BICK affect sound quality as well as clock jitter on MCLK?

[A1010] The internal delta-sigma modulator operates on MCLK. LRCK and BICK are only used for latching input/output data, therefore generally clock jitter on LRCK or BICK does not affect the sound quality.

[Q1011] How should the unused analog input pins be handled?

[A1011] Handling may differ depending upon the specific ADC device. Single-ended input devices should normally be left open to allow the pin(s) to stabilize at their self-biasing point.
Differential input devices should have their input+ and input- pins shorted together and the pair either grounded or left floating.
Each device should have specific recommendations in their respective datasheet Handling of Unused Pins section.

[Q1012] How much capacitance does the digital input pin have?

[A1012] The input capacitance will be less than 5pF.

[Q1013] Does the digital input pin have internal pull up/down resistor?

[A1013] The handling varies case-by-case of specific pins and specific devices. It will be specified in the datasheet if they have internal pull up/down resistors.

[Q1014] DC offset is added to the AD output. What is it caused by?

[A1014] Residual DC offset does occur by the conversion process and shall be evident if the digital HPF is disabled. In most cases enabling the HPF is a very satisfactory solution to eliminating this offset.

[Q1015] Do you have a circuit diagram example of external analog input buffer circuit for channel summation mode?

[A1015] Please refer to the example of circuit diagram.

[Q1016] Explain the Input Voltage specs (differential input device). For example, how are the units +/-2.8Vpp to be interpreted?

[A1016] The meaning of +/-2.8Vpp spec units is the AINxP pin (plus input of any channel's differential input pair) is to swing its AC signal voltage portion at the level of 2.8Vpp, while the AINxN pin is to swing opposite phase and stated as -2.8Vpp. It is actually most conventionally correct to state this voltage as AINxP - AINxN = 5.6Vpp total swing of the differential pair. Notice that however stated this is only the AC portion of the signal swing relative to driving the ADC to full-scale and the voltage values are not referenced to ground.
It is assumed that the proper signal conditions are to include the DC bias voltage of approx. VCOM = ~ (AVDD/2) which is to be also provided by the external buffer circuit.

[Q1017] Explain the Input Voltage specs (single-ended input device). For example, how are the units 2.8Vpp to be interpreted?

[A1017] The meaning of 2.8Vpp units the AINx pin (input of any channel) is to swing its AC signal voltage portion at the level of 2.8Vpp. Notice that this is only the AC portion of the signal swing relative to driving the ADC to full-scale and the voltage value is not referenced to ground. It is assumed that the proper signal conditions are to include the DC bias voltage of approx. VCOM = ~ (AVDD/2) which shall be provided internally by the self-biasing circuit while the signal is coupled via capacitor.

[Q1018] Can I AC couple the input signal (differential input device)?

[A1018] Generally, no, except the AK5730, AK5522 or AK5703 devices. High performance differential input devices require critical matching of the driving Op-amp circuit to the input's internal Sample and Hold circuit. The inputs do not contain any integrated self-biasing circuitry. Passive external biasing, while maybe possible, is likely to cause degraded performance, particularly THD+N.

[Q1019] Can I drive only the AINxP input signal single-ended, while not driving AINxN (differential input device)?

[A1019] Normal swing of both the AINxP input while the AINxN input is driven with opposite phase is necessary to properly drive the device to full-scale. Driving only one input signal of the differential pair will result in only -6dBFS level until abnormal distortion will occur as the level is attempted to be increased.

[Q1020] What kind of noise is Idle Noise? It is written in the power on/off sequence of the datasheet for ADC.

[A1020] Idle Noise is a digital output without input signal in normal ADC operation. It is the same output as the S/N specification.

[Q1021] Is a register access valid in power-down mode?

[A1021] Register access is not valid if PDN is LOW. However, certain devices do allow register access while the audio clocks are stopped and the device is in power-down mode automatically. Conditions for when register access is not allowed specific to each device are specified in notes at the bottom of the first page of the Register Control Interface section in the datasheet.

Related Contents

Audio DACs

  • Stereo DACs
  • Multi-channel DACs
  • Low Power DACs
 

Audio CODECs

Mono CODECs

Stereo CODECs

Multi-channel CODECs

USB/PCM CODECs

 

Digital Audio Interfaces

AK410x/AK411x series

 

Sampling Rate Converters

AK412x/AK413x series

Line Drivers/Switches

AK42xx/AK47xx series

Page Top