Sampling Rate Converters

  • Inquiry

The AK412X series is a stereo/multi-channeled sampling rate converter. It integrates a PLL or an oscillator and does not need a master clock. Therefore it greatly simplifies the system construction. The AK412X series is suitable for a data line connection of different sampling rates such as studio audio equipments, high-end car-audios and DVD recorders.

AK4128A/AK4129: High Performance 216kHz 8ch/6ch Asynchronous Sampling Rate Converter

The AK4128A and AK4129 are 8ch/6ch digital sampling rate converters. The input audio source, that is in the range of 8kHz to 216kHz sampling rate, is converted to 8kHz to 216kHz sampling rate and output. These devices support master mode and TDM data interfaces, enabling multi inputs of asynchronous stereo data. They are suitable for a data line connection of different sampling rates such as high-end car-audios and DVD recorders that needs multi-channeled function.

Part# Data
Sheet
Automotive
Qualified
SRC
Ch#
Bits Input
fs (FSI)
Output
fs (FSO)
DR Vdd Package Control IF




Bits kHz kHz dB V    
   
AK4120VF2208 to 4832 to 961173.324VSOP3-wire / HW
AK4122AVQ2248 to 9632 to 961173.348LQFP4-wire
AK4127VFYes2248 to 2168 to 2161403.330VSOPHW
AK4128AEQ8248 to 2168 to 2161403.364LQFPHW
AK4128AVQYes8248 to 2168 to 2161403.364LQFPHW
AK4129VQYes6248 to 2168 to 2161403.364LQFPHW
AK4132VTYes2248 to 968 to 481003.3 / 1.8
16TSSOPHW
AK4133VNYes2248 to 1928 to 481103.3 / 1.8
20QFNHW
AK4136VQ2328 to 3848 to 3841763.3/1.848LQFP
AK4137EQ2328 to 7688 to 7681863.3/1.848LQFP

FAQs
(Frequently Asked Questions)

Sampling Rate Converters
Questions & Answers

Questions

[Q4001] Regarding the data output, what is the output level of SDTO after outputting LSB data? 
(Indefinite, H level, L level?)

[A4001] The SDTO pin output is Low level after sending LSB data.

[Q4002] What happens to the trailing data after inputting LSB data that has longer bit length than the input bit length setting?
For example, what happens to the lower 4 bits if the input data is 24 bits when input data bit length setting is 20 bits?

[A4002] Lower LSBs are not taken into the internal SRC.

[Q4003] What happens to the SRC output when zero data is input SRC inputs with the DITHER setting ON?

[A4003] The SRC device outputs zero data.

[Q4004] How long is group delay of the AK4121A?

[A4004] Group Delay can be calculated by the following formula. It depends on the format of the output port.
1. Output format is LSB/MSB justified:
Group Delay = 55/fsi + 2.5/fso
2. Output format is I2S:
Group Delay = 55/fsi + 2.0/fso
(Sample Rate input: fsi, output: fso)
However, there are variations in group delay, the max. of 1/fsi or 1/fso depending on the data latch timing.

[Q4005] What happens if the external LRCK/BICK input stops on the AK4127? After that, will the AK4127 return to normal operation by resuming clock input (BICK, LRCK, SDTI data)?

[A4005] When LRCK/BICK input is stopped, the built-in PLL enters UNLOCK state and the SDTO output becomes zero data. At this time, the output data suddenly becomes zero, so pop noise will be generated. It is possible to avoid pop noise by soft mute function or inputting zero data. When LRCK / BICK is input again, the PLL locks and normal power-up operation is executed. Normal data can be output 100 ms after clock input.

[Q4006] How long is group delay of the AK4127?

[A4006] Group delay of the AK4127 is as follows.
Group Delay: 54/fsi + 2/fso
(fsi: sample rate of input port, fso: sample rate of output port)
However, there are variations in group delay, the max. of 1/fsi or 1/fso depending on the data latch timing.

[Q4007] What should I care about when selecting the reference clock (REFCLK) of the PLL of the AK4127?

[A4007] There are advantages if the reference clock frequency is faster. PLL is more easily locked and the lock time is quicker. 

[Q4008] Is it possible to convert TDM format data (48 KHz, 24 bits) to 4 channels of non-TDM I2S format data (44.1 KHz, 16 bit) with the AK4128A in input synchronous mode?

[A4008] Yes, this is an example of how it is variously possible to convert TDM/non-TDM, I2S/MSB/LSB justified, sample rate, and bit length.

[Q4009] Is the master clock input( IMCLK) of the input port necessary to work on the sample rate conversion on AK4128A ?

[A4009] The master clock input is not necessary to work SRC function. Data is clocked to IBICK, ILRCK.
The master clock input could be used as the master clock of the device connected to the output port in bypass mode.

[Q4010] How long is group delay of the AK4128A?
As there are "DEM", "FIR" and "SRC" functions in the block diagram, does the "FIR" block have the most of group delay?
Does group delay occur in the "DEM" or "SRC" block?

[A4010] Group delay value of the AK4128A is 54/fsi + 10/fso (typ.).
However, there are deviations of about ±1/fs. (55/fsi + 9/fso or 53/fsi + 11/fso)
Most of delay time is occurred in the FIR block (54/fsi).
There is no delay in the DEM block. The rest of delay time is generated at the SRC block (10/fso).

[Q4011] How long is group delay in the bypass mode of the AK4128A and the AK4129?

[A4011] It depends on Audio data format of input and output port.
Input port →  Output port
I2S          →  Non-I2S:  2.5/fs
I2S          →  I2S:         2.0/fs
Non-I2S   →  Non-I2S : 3.0/fs
Non-I2S   →  I2S:         2.5/fs

[Q4012] When the AK4129 converts 24-bit input to 16-bit output, how is the remaining LSB 8 bits processed?

[A4012] The SRC block is processed with 24 bits data. However, when 16-bit output setting is selected, the result of SRC is rounded into 16 bits and output, with dither added to the LSB if dither is enabled.

[Q4013] Is the following conversion possible with the AK4129?
TDM data input (fsi = 192/96 kHz) → TDM data output (fso = 48 kHz)

[A4013] The AK4129 supports TDM mode, but does not support fs 192KHz and 96KHz. The maximum sample rate is up to 48 kHz in TDM mode for both input and output ports.

[Q4014] Is the following conversion possible with the AK4129?
2x asynchronous TDM data input (fsi = 48 kHz) → TDM data output (fso = 96 kHz)

[A4014] The AK4129 does not support two asynchronous TDM input sources. The sample rate at the output port is also out of spec.

[Q4015] Is the following conversion possible with the AK4129?
TDM data input (fsi = 48 kHz) + I2S 2ch data input (fsi = 48 kHz) (Input sources are asynchronous)→ TDM data output (fso = 96 kHz)

[A4015] The AK4129 does not support TDM and I2S at the same time on the same port. The sample rate at the output port is also out of spec.

[Q4016] Is the following conversion possible with the AK4129?
3 x I2S data input (fs 48 kHz) → TDM data output (fs 192 kHz)

[A4016] The AK4129 does not support 192kHz in TDM format on the output port. The output port supports TDM format up to fso = 48kHz. Three streams of I2S format data on the input port are available in both synchronous and asynchronous mode.

[Q4017] The AK4129 supports 32-bit BICK/data slot in TDM format in the specifications. Is 24-bit BICK/data slot supported in TDM mode?

[A4017] The AK4129 supports only 32-bit BICK/data slot in TDM mode.

[Q4018] The datasheet says "it should be reset by the PDN pin or RSTN bit in serial control mode" when external clock is changed. Without PDN pin/RSTN bit setting, what happens with the output of the AK4129?

[A4018] The AK4129 may generate pop noise when the external clock is changed without PDN pin/RSTN bit setting. An alternative way to avoid pop noise is to put the AK4129 into mute state when changing clocks.

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