Industrial AFEs & ADCs

Zero latency Delta Sigma ADC is a new concept of A/D converters with both SAR's high accuracy and Delta Sigma's high linearity.

AKM lines up A/D converters from 12-bit to 18-bit and Analog Front Ends from 12-bit to 16-bit mainly with 2 channels devices.  AKM provides optimal solutions that contribute to high precision, small size and high speed of customer’s system in a wide range of industrial applications such as a motor system and a measurement system.

Lineup

Lineup

ZDS-NS A/D Converter

NEW AK925XSeries
ZDS-NS A/D Converter

The AK925X series is a lineup of ZDS-NS (Zero latency Delta Sigma with Noise Suppression) A/D converter.
The AK925X suppresses high frequency noise in analog input signals by oversampling A/D conversion.
The AK925XA series that is a different output format option is available too.
Please visit here for details.

The AK9255NK, the AK9256NK, the AK9255ANK and the AK9256ANK are pin compatible each other.

AK9255NK
ZDS-NS A/D Converter AK9255NK
Part#SampleMass ProductArchitectureCh#BitsSpeedInterfacePower supplyPackage
AK9255NKAvailableCY2018/Q2ZDS-NS216bit1.0MSPS1Latency3.0~3.6VQFN 3mm□
AK9256NKCY2018/Q1CY2018/Q2ZDS-NS214bit1.1MSPS1Latency3.0~3.6VQFN 3mm□
AK9255ANKAvailableCY2018/Q2ZDS-NS216bit0.5MSPS0Latency3.0~3.6VQFN 3mm□
AK9256ANKCY2018/Q1CY2018/Q2ZDS-NS214bit0.6MSPS0Latency3.0~3.6VQFN 3mm□

AFE with A/D Converter

NEW AK924x Series
ZDS AFE with A/D Converter
SAR AFE with A/D Converter

The AK924X series is a lineup of ZDS (Zero latency Delta Sigma) and SAR (Successive Approximation Register) analog front ends with A/D converter.  The AK924X has a programmable gain amplifier (PGA) and low pass filter.  Therefore, sensors in various signal ranges can be connected directly.  In addition, it has a transimpedance amplifier enabling to connect with current output sensors.

The AK9243NK is pin compatible with the AK9242NK.

AK9242
AFE AK9242NK
Part#SampleMass ProductArchitectureCh#BitsSpeedPGAPower supplyPackage
AK9242NKAvailableAvailableZDS216bit1.1MSPS14~35dB4.2~5.5VQFN 4mm□
AK9243NKCY2018/Q3CY2018/Q4ZDS214bit1.1MSPS14~35dB4.2~5.5VQFN 4mm□
AK9240NKAvailableCY2018/Q1SAR212bit1.0MSPS14~35dB2.7~5.5VQFN 3mm□

Single Function A/D Converter

AK923x Series
ZDS A/D Converter, SAR A/D Converter

The Ak923x series is a lineup of single function ZDS (Zero latency Delta Sigma) and SAR (Successive Approximation Register) A/D converters.  They are low input capacitance devices that can be easily adopted to your system.  With a product that has 14-bit or more resolution, it is more difficult to derive the A/D converter characteristics.  Therefore, ZDS architecture is adopted for these products for a longer acquisition time.

The AK9232NK, the AK9233NK and the AK9234NK are pin compatible each other.
The AK9235NK is pin compatible with the AK9255NK, the AK9256NK, the AK9255ANK and the AK9256ANK.

AK9232
ZDS A/D Converter AK9232NK
Part#SampleMass ProductArchitectureCh#BitsSpeedInput Cap.Power supplyPackage
AK9232NK AvailableAvailableZDS218bit1.1MSPS32pF4.75~5.25VQFN 4mm□
AK9233NK AvailableAvailableZDS216bit1.1MSPS32pF4.75~5.25VQFN 4mm□
AK9234NK AvailableAvailableZDS214bit1.1MSPS32pF4.75~5.25VQFN 4mm□
AK9235NK AvailableCY2018/Q2SAR212bit1.0MSPS13pF3.0~5.5VQFN 3mm□

ΔΣ Modulator

AK922x Series
ΔΣ Modulator

The AK922X series is a line-up of single function Delta-sigma modulators.  The AK922X outputs 1-bit Pulse Density Modulation signal by oversampling A/D conversion.  High resolution and linearity can be achieved by demodulating low frequency signals by suppressing high frequency signals with a digital filter at the output stage of the AK922X.

AK9223MK
ΔΣ A/D Converter AK9223MK
Part#Sample Mass ProductArchitectureCh#BitsSpeedOutput FormatPower supplyPackage
AK9223MK AvailableAvailableDelta-Sigma21bit10MSPSModulator4.5~5.5VTSSOP

Selection Table

Part# Data
Sheet
Ch# Resolution Speed Vdd Power
Consumption
Interface Size Package Others


Ch bits MSPS V mW
mm(mm2)

   
AK9223MK2160.045.0/3.067.5Serial4.4×7.8(50)24TSSOPModulator
AK9232NK2181.15.0/3.0/1.8200SPI4×4 (16)24QFNInternal Vref/Polar coordinate calclation
AK9233NK2161.15.0/3.0/1.8200SPI4×4 (16) 24QFNInternal Vref/Polar coordinate calclation
AK9234NK2141.15.0/3.0/1.8200SPI4×4 (16)24QFNInternal Vref/Polar coordinate calclation
AK9235NK
2121.05.0/3.031SPI3x3 (9)16QFN
AK9240NK
21215.0/3.083SPI3×3 (9)20QFNTIA/PGA/LED Driver/Internal Vref/APC/LPF
AK9242NK
2161.15.0/3.0505SPI4×4 (16)24QFNTIA/PGA/Internal Vref/Polar coordinate calculation/LPF
AK9243NK
2141.15.0/3.0505SPI4×4 (16)24QFNTIA/PGA/Internal Vref/Polar coordinate calculation/LPF
AK9255ANK
2160.53.3/3.388SPI3x3 (9)16QFNNoise Suppression
AK9255NK
2161.03.3/3.388SPI3x3 (9)16QFNNoise Suppression
AK9256ANK
2140.63.3/3.388SPI3x3 (9)16QFNNoise Suppression
AK9256NK
2141.13.3/3.388SPI3x3 (9)16QFNNoise Suppression

[Note]

*TIA:  Trans Impedance Amplifier

*PGA:  Programmable Gain Amplifier


* Sample and product release dates may be subject to change without notice.

* Preliminary datasheet is subject to change without notice.

Technical information

Technical Information

ZDS
(Zero latency Delta Sigma)

Even if a high-precision A/D converter is used, the system accuracy cannot be improved unless the sensor output signal is sampled with high accuracy.
However, it is not easy to realize high precision sampling at the beginning of acquisition of the A/D converter since signal swing called "kickback" occurs.

"ZDS" resolves this problem.
High accurate sampling is easily achieved with a ZDS A/D converter.

[Point-1]
Small Input Capacitance = Small Kickback

With an SAR A/D converter, its input capacitance increases as the accuracy of the A/D converter become high, and the kickback level increases.

A ZDS A/D converter makes high precision sampling easier because the input capacitance and the kickback level are lower than an SAR A/D converter.

[Point-2]
Long Acquisition Time = Long Recovery Time from Kickback

An SAR A/D converter cannot execute conversion and acquisition at the same time.
Therefore, the faster the response of the A/D converter, the shorter the acquisition time becomes.

A ZDS A/D converter realizes executing acquisition during conversion.  In other words, the A/D converter increases the recovery time from kickback while keeping fast response ability, enabling high precision sampling that is essential for high accuracy system.

ZDS-NS
(Zero latency Delta Sigma with Noise Suppression)

Even if a low-noise A/D converter is used, system noise level cannot be improved unless the input signal noise is reduced. However, it is not easy to generate low noise analog signals with a system that accomplishes high speed response performance.

"ZDS-NS" resolves this problem.
ZDS-NS A/D converter realizes high-speed response while suppressing input signal noise.

Frequency Response Gain of ZDS-NS Digital Filter

The magnitude plot of the ZDS-NS digital filter is shown here.
Since the A/D conversion of ZDS-NS is executed by over sampling that is in the same way as ΔΣ, high frequency noise components up to 10 MHz (* 1) included in the analog input signal are also converted and attenuated by the integrated digital filter. Furthermore, noise suppression effect can be improved by increasing the number of over sampling.

(*1) It is proportional to clock frequency.

ZDS-NS can suppress noise included in the input signal while maintain fast response, realizing both low-noise and high speed response performances on the system.

General Purpose Analog Front End

The general-purpose analog front end is an A/D converter with built-in peripheral circuits such as programmable gain amplifier.  With a general-purpose analog front end, AKM makes your system smaller, faster and more accurate.

Design Support

Design Support

Evaluation Tools (Board & Software)

An evaluation board that integrates necessary peripheral circuits for an A/D converter is available onerously.  To obtain evaluation tools, please contact us from the Inquiry Form and select “Industrial LSI” in the product category.

Evaluation Board

An evaluation board integrates necessary peripheral circuits for the A/D converter.  Easy evaluation of an A/D converter is available by just inputting a signal and power to the connectors.

In addition, evaluation software and a FPGA board that can be connected to a PC are also available.

AK9232
AKD9242μB

Evaluation Software

Use evaluation software on a PC by connecting an FPGA board.

AK9232
Software Example
Part#Evaluation
Board
Part#
Evaluation Kit
(FPGA Board)
Status
AK9223MKAKD9223μBAKD9223DCBAvailable
AK9232NKAKD9232AKD9232DCBAvailable
AK9233NKAKD9233AKD9233DCBAvailable
AK9234NKAKD9234AKD9234DCBAvailable
AK9235NKAKD9235AKD9235DCBCY2017/Q4
AK9242NKAKD9242μBAKD9242DCBAvailable
AK9243NKAKD9243μBAKD9243DCBCY2018/Q3
AK9240NKAKD9240μBAKD9240DCBAvailable
AK9255NKAKD9255μBAKD9255DCBCY2017/Q4
AK9255ANKAKD9255AμBAKD9255ADCBCY2017/Q4
AK9256NKAKD9256μBAKD9256DCBCY2017/Q4
AK9256ANKAKD9256AμBAKD9256ADCBCY2017/Q4

FAQ

FAQ
(Frequently Asked Questions)
Industrial AFEs/ADCs
Questions & Answers

Questions

Common

[Q9001] Are there any restrictions in power-on sequence?

[A9001] It depends on the product.  Please refer to the 【System Reset】 paragraph in each product datasheet.  If there is no particular description in the datasheet, it does not have a restriction.

[Q9002] Can 2-channel data be sampled at the same time?

[A9002] Yes, it is possible.  Two ADCs are integrated in the device and sampling can be executed simultaneously.

[Q9003] What temperature is the recommended operating temperature described in the data sheet?

[A9003] It is indicating ambient temperature.

[Q9004] Does the thermal pad have to be connected?

[A9004] It depends on the product.  Please refer to the 【Package】 paragraph in the datasheet of each product.

[Q9005] What is the output circuit system?

[A9005] It is CMOS type.  The AK9223MK also supports TTL type.

[Q9006] Is reference design available?

[A9006] Yes, it is.  Please refer to 【Application Notes】 for details.

[Q9007] If the number of decoupling capacitors is reduced from the number shown in the data sheet or if the capacitance value is decreased, is there any effect on the characteristics?

[A9007] Yes, it will affect the characteristics.  We cannot guarantee the characteristics in that case.  Connection example in the datasheet is recommended.

[Q9008] Is it possible to eliminate the low pass filter on the preceding stage of the ADC input?

[A9008] It depends on the product series.
<AK922X,AK923X>
No, it is not possible.  Since the RC filter on the preceding stage of the analog input also works as kickback protection from the ADC, it is necessary to exceed the recommended value described in the data sheet.
<AK924X>
Yes, it is possible.  A 250 kHz LPF is built in as default.  It can be changed to 100 kHz by register setting.  When much lower band LPF is required, it is necessary to set a low pass filter separately at signal input circuit.

[Q9009] Are there any recommended op-amp products?

[A9009] Yes, there are.  The AK2975H and so on.  Please visit here for details.

[Q9010] Is a simple evaluation tool available?

[A9010] Yes, it is.  Various evaluation boards are available.  Please refer to 【Evaluation Kit】 for details.

[Q9011] Is FPGA source code available?

[A9011] No, we do not provide it at the moment.

AFEs with A/D Converter
AK924x

[Q9101] Is it possible to read normal output data simultaneously in polar coordinate output mode?

[A9101] No, it is not possible.  In polar coordinate output mode, "angle" and "moving radius" data is output, and data of normal output mode cannot be output.  It will be in the same manner in normal output mode.

[Q9102] How is it calculated in polar coordinate output mode?

[A9102] It is calculated by CORDIC (Coordinate Rotation Digital Computer).  CORDIC is an algorithm for finding mathematical functions like trigonometric function by only adding and subtracting.

[Q9103] Tell me about the structure of current input circuit.

[A9103] It is composed by a transimpedance amplifier.  Please refer to “Current Input Mode” paragraph of functional descriptions in datasheet.

[Q9104] Once you write a register setting, will it be automatically reflected on reboot after stopping the power supply?

[A9104] No, it will not be reflected automatically.  Make sure to write desired registers upon power-up or after reset.

[Q9105] Is it possible to connect the register WRITE pin and READ pin to the I/O port together?

[A9105] Yes, it is possible.

[Q9106] Is it possible to adjust offset, gain, and phase for each sampling?

[A9106] Yes, it is possible.  They can be adjusted by updating each register value by SPI communication.  Since it is a register setting, it is also possible to change the correction amount at an arbitrary timing.

[Q9107] Are offset, gain and phase correction are executed automatically?

[A9107] No, they are not.  It is necessary to write an arbitrary setting value to the register.

[Q9108] Is there any way to reduce current consumption?

[A9108] Yes.  Please refer to 【Application Notes】 for details.

[Q9109] Can CSN and SCLK be used asynchronously?

[A9109] No, it is not possible.  These signals must be used in synchronous operation.

[Q9110] Are both High and Low states of SCLK accepted at CSN Low edge?

[A9110] It depends on the product.
<AK9242NK,AK9243NK>
No.  In the case of the timing shown below, MSB data will not be output if SCLK is Low on the falling edge of CSN.  Therefore, the SCLK signal must be High on the falling edge of CSN.

A9020

<AK9240NK> Yes, both states are accepted.

[Q9111] Is SCLK input necessary during High period of CSN?

[A9111] No, it is not necessary.  However, SCLK state must be set according to the question [Q9110].

[Q9112] Is there any way to reduce digital wiring?

[A9112] Yes, there are various methods depending on the products.  Please refer to 【Application Notes】 for details.

Single Function A/D Converter
AK923x

[Q9201] Is it possible to read normal output data simultaneously in polar coordinate output mode?

[A9201] No, it is not possible.  In polar coordinate output mode, "angle" and "moving radius" data is output, and data of normal output mode cannot be output.  It will be in the same manner in normal output mode.

[Q9203] How is it calculated in polar coordinate output mode?

[A9203] It is calculated by CORDIC (Coordinate Rotation Digital Computer).  CORDIC is an algorithm for finding mathematical functions like trigonometric function by only adding and subtracting.

[Q9204] Once you write a register setting, will it be automatically reflected on reboot after stopping the power supply?

[A9204] No, it will not be reflected automatically.  Make sure to write desired registers upon power-up or after reset.

[Q9205] Is it possible to connect the register WRITE pin and READ pin to the I/O port together?

[A9205] Yes, it is possible.

[Q9206] Is it possible to adjust offset, gain, and phase for each sampling?

[A9206] Yes, it is possible.  They can be adjusted by updating each register value by SPI communication.  Since it is a register setting, it is also possible to change the correction amount at an arbitrary timing.

[Q9207] Are offset, gain and phase correction are executed automatically?

[A9207] No, they are not.  It is necessary to write an arbitrary setting value to the register.

[Q9208] Is there any way to reduce current consumption?

[A9208] Yes.  Please refer to 【Application Notes】 for details.

[Q9209] Can CSN and SCLK be used asynchronously?

[A9209] No, it is not possible.  These signals must be used in synchronous operation.

[Q9210] Are both High and Low states of SCLK accepted at CSN Low edge?

[A9210] It depends on the product.
<AK9232NK,AK9233NK,AK9234NK>
No.  In the case of the timing shown below, MSB data will not be output if SCLK is Low on the falling edge of CSN.  Therefore, the SCLK signal must be High on the falling edge of CSN.

A9020

[Q9211] Is SCLK input necessary during High period of CSN?

[A9211] No, it is not necessary.  However, SCLK state must be set according to the question [Q9210].

[Q9212] Is there any way to reduce digital wiring?

[A9212] Yes, there are various methods depending on the products.  Please refer to 【Application Notes】 for details.

ΔΣ Modulator
AK922x

[Q9301] Is it possible to set the sampling frequency of AK9223MK to 20 MHz?

[A9301] No, it is not possible.  The maximum sampling rate will be 10 MHz since the AK9223MK internally divides clock (CLKI/2) in external CLK mode.

Selection Guide

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