AK4679EG

24bit Stereo CODEC with DSP and MIC/RCV/HP/SPK/LINE-AMP

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概要

The AK4679 is a 24bit stereo CODEC and a built-in Microphone-Amplifier, Receiver-Amplifier, Mono Class-D Speaker-Amplifier, Cap-less Class-G Headphone-Amplifier and Line-Amplifier as well as HF/Audio DSP. The AK4679 features AKM DSP core to deal with hands free function for wide band and dual PCM I/F in addition to audio I/F that allows easy interfacing in mobile phone designs with Bluetooth I/F. The playback features also include 5-band Parametric EQ and Dynamic Range Control; therefore the AK4679 can automatically adjust the volume to a comfortable level that has no distortion and provides great flexibility. The AK4679 is available in a 78pin BGA, utilizing less board space than competitive offerings.

特長

CODEC&Amp block

1. Recording Function (Stereo CODEC)

• 4 Stereo Input Selectors

• 4 Stereo Inputs (Single-ended) or 3 Mono Input (Full-differential)

• MIC Amplifier: +24dB to -6dB, 3dB step

• 2 Output MIC Power Supplies

• Digital ALC (Automatic Level Control): +36dB to -54dB, 0.375dB Step, Mute

• ADC CHARACTERISTICS: S/(N+D): 80dB, DR, S/N: 87dB (MIC-Amp=+18dB)

S/(N+D): 80dB, DR, S/N: 92dB (MIC-Amp=0dB)

• Stereo Digital MIC Interface

• Wind-noise Reduction Filter

• Stereo Separation Emphasis

• 3-band Programmable Notch Filter

• Audio Interface Format: 24/16bit MSB justified, 24/16bit I2S, 16bit DSP Mode

2. Playback Function (Stereo CODEC)

• Digital Volume (+6dB to -57.0dB, 0.5dB Step, Mute)

• Digital ALC (Automatic Level Control): +36dB to -54dB, 0.375dB Step, Mute

• Stereo Separation Emphasis

• Dynamic Range Control

• 5-band Parametric Equalizer

• Stereo Line Output (Selectable Full-differential / Single-ended)

• Mono Receiver-Amp

- BTL Output

- Output Power: 60mW @ 32Ω

- Analog Volume: +12 to -30dB & Mute, 3dB Step

• Cap-less Stereo Class-G Headphone-Amp

- Output Power: 25mW @ 32Ω, 45mW @ 16Ω

- Analog Volume: +6 to -62dB & Mute, 2dB Step

- Zero crossing Detection

- Pop Noise Free at Power-ON/OFF

• Mono Class-D Speaker-Amp

- BTL Output

- Short Protection Circuit

- Output Power: 1.1W @ 8Ω, SVDD=4.2V, THD+N = 10%

0.89W @ 8Ω, SVDD=4.2V, THD+N = 1%

- Analog Volume: +12 to -30dB & Mute, 3dB Step

- Pop Noise Free at Power-ON/OFF

• Audio Interface Format:

- 24/16bit MSB justified, 16bit LSB justified, 16/24bit I2S, 16bit DSP Mode

3. Dual PCM I/F for Baseband & Bluetooth Interface

• Four sample Rate Converters (Up sample: up to x6: Down sample: down to x1/6)

• Sample Rate:

- PORTA (Mono): 8 to 16kHz

- PORTB (Stereo): 8 to 48kHz

• Digital Volume

• Slave Mode

• Audio Interface Format:

- 16bit Linear, 8bit A-law, 8bit µ-law

- Short/Long Frame, I2S, MSB justified

4. Power Management

5. Master Clock(Audio I/F):

(1) PLL Mode

• Frequencies: 11.2896MHz, 12MHz, 12.288MHz, 13MHz, 13.5MHz, 19.2MHz, 24MHz, 25MHz, 26MHz, 27MHz (MCKI pin)

32fs or 64fs (BICK pin)

(2) External Clock Mode

• Frequencies: 256fs, 512fs or 1024fs (MCKI pin)

6. Output Master Clock Frequencies(Audio I/F): 32fs/64fs/128fs/256fs

7. Sampling Frequency (Audio I/F)

• PLL Slave Mode (BICK pin): 8kHz to 48kHz

• PLL Master Mode: 8kHz, 11.025kHz, 12kHz, 16kHz, 22.05kHz, 24kHz, 32kHz, 44.1kHz, 48kHz

• EXT Master/Slave Mode: 8kHz to 48kHz (256fs), 8kHz to 24kHz (512fs), 8kHz to 12kHz (1024fs)

8. Audio I/F: Master/Slave mode

 DSP block

9. Embedded DSP

- Flexible programming with built-in program and data memories

- Hardware accelerator

- Word length: 24bit (Data RAM 24bit floating point)

- Multiplier 20 x 20 → 40bit (double precision available)

- Divider 20 / 20 → 20bit

- ALU: 44bit arithmetic operation (with overflow margin 4bit)

24bit floating point arithmetic and logic operation

- Program RAM: 4096w x 36bit

- Coefficient RAM: 2048w x 20bit

- Data RAM: 2048w x 24bit (24bit floating point)

- Offset Register: 32w x 15bit

- Delay RAM: 16384w x 24bit (24bit floating point)

- 5625 steps at fs16KHz, 1875 steps at fs48KHz

- Internal clock generator

10. DSP Serial Audio Interface Format

- 24bit Left justified, I2S,

- 16/24 bit linear, 8bit A-law, 8bit µ-law PCM

- Sampling rate 8 KHz to 48 KHz

- Up/Down sampling rate converter for Port#2 (8KHz → 16KHz)

11. Operational, sleep, suspend mode

 General

12. μP I/F: I2C Bus (Ver 1.0, 400kHz Fast Mode), SPI (DSP block only)

13. Ta = -30 to 85°C

14. Power Supply:

• SVDD (SPK/RCV/LINE-Amp): 3.0 to 5.5V

• AVDD (Analog): 1.7 to 2.0V

• DVDD (Digital Core): 1.7 to 2.0V

• PVDD (HP-Amp & Charge Pump): 1.7 to 2.0V

• TVDDA, TVDDE (Digital I/F): 1.6 to 3.6V

• VDDE (DSP Core): 1.1 to 1.3V

15. Package: 78pin FBGA (4.5 x 4.5 mm, 0.4mm pitch)

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ブロック図

Block Diagram

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