3.3V LVPECL 1:4 Clock Fanout Buffer
The AK8181D is a member of AKM’ｓ LVPECL clock fanout buffer family designed for telecom, networking and computer applications, requiring a range of clocks with high performance and low skew. The AK8181D distributes 4 buffered clocks.
AK8181D are derived from AKM’ｓ long-term- experienced clock device technology, and enable clock output to perform low skew. The AK8181D is available in a 20-pin TSSOP package.
Selectable differential PCLK0p/n or LVPECL clock inputs
PCLK0p/n pair can accept the following differential input levels; LVDS, LVPECL, LVHSTL, SSTL, HCSL
PCLK1p/n supports the following input types; LVPECL, CML, SSTL
Clock output frequency up to 650MHz
Translates any single-ended input signal to 3.3V LVPECL levels with resistor bias on PCLK0n input
Output skew : 30ps maximum
Part-to-part skew : 150ps maximum
Propagation delay : 1.5ns maximum
Additive phase jitter(RMS) : 0.040ps (typical)
Operating Temperature Range: -40 to +85℃
Package: 20-pin TSSOP (Pb free)
Pin compatible with ICS8533I-01