16 bit 35 MSPS/ch 3ch video ADC & CCD interface with internal TG

  • Inquiry


The AK8442A comprises an A/D converter consisting of a 3.3 V 16 bit 3-channel 35 MSPS/ch CMOS with integrated CDS circuitry and TG for linear CCD drive. It is optimized for scanner and copier applications.

Key Features



D-Range 1.77 Vpp / 2.35 Vpp (typ.)

• 3ch. sampling : CDS circuit (Correlated Double Sampling)

• Input polarity : Negative polarity only


Max. Conversion Rate 16 bits 3ch: 8 ~ 35 MSPS/ch.

16 bit 2ch: 8 ~ 35 MSPS/ch

10 bit mode: 8 ~ 40 MSPS/ch

Resolution 16 bit (straight binary code)

• Offset DAC : Separate 3 channel 8bit DAC

With automatic black offset loop.

Range: 375mV

• PGA (Programmable Gain Amp.)

Range 0 ~ 21.3 d B

Resolution 7bit

• LVDS output

16bit 3ch.in order of serial output ADC: 35MSPS, 105M output rate

16bit 2ch.in order of serial output ADC: 35MSPS, 70M output rate

10bit 3ch.serial output ADC: 40MSPS, 40M output rate

LVDS operating range 16M ~ 105M

LVDS will be double data rate output when LVDS clock under 16MHz.

• Timing Generator

TG Output Terminal TG1 ~ 15

Max. Pixel Rate 35MHz (40M@10bit mode)

Internal Shift Pulse 10sets (SH0 ~ 9)

Internal Transfer Pulse 2sets (P0, P1)

Pixel Rate Pulse 2sets (PCL, PRS)

Time Resolution Pixel Cycle 1/48

• Power Supply 3.0~3.6V

• CPU I/F 4 line Serial Interface (R/W , Address Bank Switch)

• Power Consumption 1.09mW (Typ.) @35MHz3ch, 16bit mode

• Operation Temperature: 0 ~ 70°C

• Package: 80pin LQFP (Pin pitch 0.5mm) , 12mm×12mm

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