FAQ - 数字音频接口

数字音频接收器的主频工作模式 (CM bits) 在Mode0和Mode2状态下有什么不同?

[Q0082]

回答

RX输入停止 (Unlock状态) 时PLL时钟源不同。
Mode0: PLL以自由运行的时钟运行
Mode2: PLL由外部XTAL时钟运行

AK4118可以接收DoP格式的信号吗?

[Q0083]

回答

可以接收DoP格式的信号。

如果RX输入管脚没有信号输入时,音频输出会如何?

[Q0084]

回答

在没有输入信号,或者输入信号不支持S/PDIF格式的情况下,Clock Recovery模块中的PLL将处于Unlock状态。
Clock mode 0 (CM[1:0] = 00) 模式时,在音频I/F上输出自由运行的时钟 (free running clock) (MCLKO1=1.5 ~ 5.0MHz) 
Clock mode 2 (CM[1:0] = 10) 模式时,IC将根据输入到XTI引脚的时钟输出

如果完全相同的音频信号同时输入给两个AK4115系统,那么两个系统的Audio I/F输出和DIT输出会存在相位差吗?

[Q0085]

回答

由于内部时序取决于外部输入 (RX, TX的音频 I/F)信号,因此如果输入信号时序相同的话,就不会出现输出相位差。AK4118A也是同样。

如果AK4115的RX和TX在非同期模式下同时工作时B、C、U输出引脚会输出RX信号吗?

[Q0086]

回答

AK4115在非同期模式下 (ASYNC bit="1") 工作时,如果B、C、U设定为输出引脚 (BCU_IO bit= "1", BCU bit="1") 的话,DIT会定期出现异常现象,但DIR会正常工作。
如果需要DIR和DIT同时工作的话,

(1) 将B、C、U引脚配置为输入设置 (BCU_IO bit= "0")
或者,
(2) 将B、C、U引脚配置为低电平输出 (BCU bit="0")

在此设置下B、C、U管脚不能用于DIR的模块启动,通道状态和用户数据监控功能。

FAQ - 数字音频接口

Digital Audio Interfaces

[Q0082]
・What is the difference between Master Clock Operation Mode 0 and Mode 2 of the Digital Audio Receiver products line?
A.
・PLL clock source when RX input is stopped (UNLOCK state) is different.
Mode 0: PLL is operated on free running clock.
Mode 2: PLL is operated by an external XTAL clock.
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[Q0083]
・Can the AK4118A accept DoP format signals?
A.
・Yes, it can. DoP data can be transferred without any change in format.
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[Q0084]
・What is the output signal of Audio I/F if there is no input signal to the receiver input channels (RX)?
A.
・The PLL in the clock recovery block will be in Unlock state if there is no input signal or the input signal does not support S/PDIF format. 
 In Clock Mode 0 (CM[1:0] = 00) the device outputs as free running clock on the Audio I/F (MCLK01 ~= 1.5MHz ~ 5MHz). 
 In Clock Mode 2 (CM[1:0] = 10) the device will output the clock according to the clock input to the XTI pin.
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[Q0085]
・If exactly the same signals are input to the two AK4115's that are used in the same system, will a phase shift occur between DIT output and Audio I/F output of each devices?
A.
・Since the internal timing depends on the external input (RX, Audio I/F for TX) signal, the phase shift between two devices does not occur at the the receiving part (RX) and the transmitting part (TX).
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[Q0086]
・When RX and TX path in the AK4115 are operated in asynchronous mode at the same time, are B, C, U signals for RX path outputted?
A.
・In the case that the AK4115 operates in the asynchronous mode (ASYNC bit = "1"), DIT function periodically becomes abnormal if the B, C, U pins are set as output (BCU_IO bit = 1, BCU bit = 1). 
On the other hand, the DIR operates normally. 
To realize simultaneous operation with DIR and DIT,
(1) the B, C, U pins should be configured to input setting (BCU_IO bit = 0),
 or 
(2) set the B, C, U pins to low output setting (BCU bit=0).
The B, C, U pins cannot be used for Block-Start, Channel Status and User Data Monitoring functions of the DIR on this setting.
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