FAQ - 采样率转换器

关于数据输出格式,输出LSB数据后,SDTO的输出电平会如何? (不定、高电平、还是低电平?) 

[Q0062]

回答

输出LSB数据后SDTO管脚输出低电平。

如果输入数据位数长于数据长度,下位数据会怎样?
比如,输入数据位数长度是20bit,但是如果输入24bit的数据的话,下位4位被如何处理?

[Q0063]

回答

下位数据不会被使用。

在DITHER ON设定下,如果输入Zero 数据,那么SRC输出会如何?

[Q0064]

回答

SRC会输出Zero数据。

AK4121A的群延迟是多少?

[Q0065]

回答

群延迟可以通过如下算式计算出。计算式根据输出格式不同会不同。
1. Output Format: LSB/MSB justified时,Group Delay=55/fsi+2.5/fso
2. Output Format: I2S时,Group Delay =55/fsi+2.0/fso 
 (采样率输入: fsi,输出: fso) 
但请注意实际上群延迟会存在最大1fsi 或 1fs左右的误差。

如果停止提供LRCK/BICK会出现什么情况?如果再次提供正常输入信号 (BICK、LRCK、SDTI data) 的话,AK4127会返回正常工作吗?

[Q0066]

回答

如果停止输入LRCK/BICK,PLL将处于Unclock状态,SDTO输出“0”。由于输出电平突然变为“0”,因此会出现POP噪声。请使用Softmute功能,或者输入“0”数据来回避POP噪声。之后再次供给LRCK/BICK,PLL会自动锁定,IC正常启动,并且在输入时钟100ms以后输出正常数据。

AK4127的群延迟是多少?

[Q0067]

回答

AK4127的群延迟如下。
Group Delay:54/fsi+2/fso 
 (采样率输入: fsi,输出:fso)
但实际上群延迟会存在最大1fsi 或 1fso左右的误差。

如何选择AK4127的PLL参考时钟 (REFCLK)?

[Q0068]

回答

REFCLK 频率越高,PLL越容易锁定,锁定时间也会越短。

在同步模式下,能否将AK4128输入的TDM格式数据 (48kHz, 24bit) 转换为4通道I2S格式数据 (44.1kHz, 16bit)?

[Q0069]

回答

采样率和bit长度都可以转换。

AK4128A是否需要输入Master Clock (IMCLK) 才能工作?

[Q0070]

回答

IMCLK不是必须条件。可以通过IBLK、ILRCK采集数据。IMCLK时钟可以作为连接到SRC输出端口的转换器的主时钟。

AK4218A的群延迟是多少?框图中表示的"DEM","FIR" 和"SRC" 模块中,"FIR"模块是否是决定群延迟的主要因素?"DEM" 和 "SRC"模块存在迟延吗?

[Q0071]

回答

AK4128A的输出延迟为: 64/fs=54/fsi+10/fso。注意存在1/fs左右的误差。
 (55/fsi+9/fso 或53/fsi+11/fso) 
输入端的延迟主要来自"FIR"模块 (54/fsi)。"DEM"模块不存在延迟。"SRC" 模块的延迟为10/fso。

AK4127、AK4128A、AK4129芯片在Bypass模式设定时的群延迟是多少?

[Q0072]

回答

ILRCK 和OLRCK同相位的条件下,群延迟与输出音频数据格式有关。
输入 → 输出
I2S → LSBJ/MSBJ :  1.5/fs 
I2S → I2S :  1.0/fs 
LSBJ/MSBJ → LSBJ/MSBJ :  1.0/fs 
LSBJ/MSBJ → I2S :  0.5/fs 
请注意,以上的群延迟存在±1fs左右的误差。

AK4129进行输入24bit → 输出16bit变换时,LSB的8bit被怎么处理?

[Q0073]

回答

SRC模块是以24bit数据进行处理的。如果选择16bit输出的话,SRC的结果被四舍五入为16bit后输出。

AK4129是否可以进行如下变换?
TDM data input (fs=192/96kHz) → TDM data output (fs=48kHz)

[Q0074]

回答

此变换在TDM模式下可以支持。最大采样率为48kHz。

AK4129是否可以进行如下变换?
TDM data input (fs=48kHz) + TDM data input (fs=48kHz) → TDM data output (fs=96kHz)
 (TDM数据是非同步输入) 

[Q0075]

回答

AK4129不支持2个非同步TDM输入源的变换。并且输出fs也不在定义范围内。

AK4129是否可以进行如下变换?
TDM data input (fs=48kHz) + I2S 2ch data input (fs=48kHz) → TDM data output (fs=96kHz) 
(2个输入信号非同步)

[Q0076]

回答

AK4129不支持同时输入TDM和I2S 的变换。并且输出端fs也不在定义范围内。

AK4129是否可以进行如下变换?
I2S x 3 data input (fs=48KHz) → TDM data output (fs=192KHz)

[Q0077]

回答

在TDM输出格式下,AK4129仅支持fs=48kHz,并不支持fs=192kHz。另外,输入端支持同期或非同期模式。

AK4129支持32bit/slot TDM格式,是否也支持24bit/slot TDM格式?

[Q0078]

回答

AK4129仅支持32bit/slot TDM格式。

AK4129数据手册中记载着,在切换时钟时需要先将IC Power down 或者RSTN bit=0。如果不进行Power down或者Reset的话会有什么影响?

[Q0079]

回答

如果切换时不进行Power down的话,有可能会输出Pop噪声。
为了消除Pop噪声,可以使用Mute功能进行时钟切换,切换时先对IC进行Mute然后再变更频率。 (Mute时间以及解除方法等请参考数据手册) 

如果使用1个AK4128A对输入8ch进行同步操作的话,输出的8ch之间会产生相位偏移吗?

[Q0080]

回答

8ch的输出之间不会产生相位偏移。

如果使用2个AK4128A对输入16ch进行同步操作的话,输出的16ch之间会产生相位偏移吗?

[Q0081]

回答

有出现相位偏差的可能性。AK4128A SRC模块的工作时钟是内置OSC。所以即使外部时钟 (BICK、ILRCK、OBICK、OLRCK)是同样的,每个内置OSC的工作频率也会存在偏差。这样频率转换时序就会产生偏差,导致2个SRC输出相位存在偏差。

FAQ - 采样率转换器

Sample Rate Converters

[Q0062]
・Regarding the data output, what is the output level of SDTO after outputting LSB data? 
(Indefinite, H level, L level?)
A.
・The SDTO pin output is Low level after sending LSB data.
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[Q0063]
・What happens to the trailing data after inputting LSB data that has longer bit length than the input bit length setting? 
 For example, what happens to the lower 4-bit if the input data is 24-bit when input data bit length setting is 20-bit?
A.
・Lower LSBs are not taken into the internal SRC.
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[Q0064]
・What happens to the SRC output when zero data is input SRC inputs with the DITHER setting ON?
A.
・The SRC device outputs zero data.
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[Q0065]
・How long is group delay of the AK4121A?
A.
・Group Delay can be calculated by the following formula. It depends on the format of the output port. 
 1. Output format is LSB/MSB justified: 
Group Delay = 55/fsi + 2.5/fso 
 2. Output format is I2S: 
Group Delay = 55/fsi + 2.0/fso 
 (Sample Rate input: fsi, output: fso) 
 However, there are variations in group delay, the max. of 1/fsi or 1/fso depending on the data latch timing.
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[Q0066]
・What happens if the external LRCK/BICK input stops on the AK4127? After that, will the AK4127 return to normal operation by resuming clock input (BICK, LRCK, SDTI data)?
A.
・When LRCK/BICK input is stopped, the built-in PLL enters UNLOCK state and the SDTO output becomes zero data. At this time, the output data suddenly becomes zero, so pop noise will be generated. It is possible to avoid pop noise by soft mute function or inputting zero data. When LRCK / BICK is input again, the PLL locks and normal power-up operation is executed. Normal data can be output 100 ms after clock input.
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[Q0067]
・How long is group delay of the AK4127?
A.
・Group delay of the AK4127 is as follows. 
 Group Delay: 54/fsi + 2/fso 
 (fsi: sample rate of input port, fso: sample rate of output port) 
 However, there are variations in group delay, the max. of 1/fsi or 1/fso depending on the data latch timing.
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[Q0068]
・What should I care about when selecting the reference clock (REFCLK) of the PLL of the AK4127?
A.
・There are advantages if the reference clock frequency is faster. PLL is more easily locked and the lock time is quicker.
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[Q0069]
・Is it possible to convert TDM format data (48 KHz, 24-bit) to 4 channels of non-TDM I2S format data (44.1 KHz, 16-bit) with the AK4128A in input synchronous mode?
A.
・Yes, this is an example of how it is variously possible to convert TDM/non-TDM, I2S/MSB/LSB justified, sample rate, and bit length.
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[Q0070]
・Is the master clock input (IMCLK) of the input port necessary to work on the sample rate conversion on AK4128A ?
A.
・The master clock input is not necessary to work SRC function. Data is clocked to IBICK, ILRCK. 
The master clock input could be used as the master clock of the device connected to the output port in bypass mode.
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[Q0071]
・How long is group delay of the AK4128A? 
As there are "DEM", "FIR" and "SRC" functions in the block diagram, does the "FIR" block have the most of group delay? 
Does group delay occur in the "DEM" or "SRC" block?
A.
・Group delay value of the AK4128A is 54/fsi + 10/fso (typ.). 
However, there are deviations of about ±1/fs. (55/fsi + 9/fso or 53/fsi + 11/fso) 
Most of delay time is occurred in the FIR block (54/fsi). 
There is no delay in the DEM block. The rest of delay time is generated at the SRC block (10/fso).
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[Q0072]
・How long is group delay in the bypass mode of the AK4127, AK4128A and the AK4129?
A.
・It depends on Audio data format of input and output port on the condition of the same phase between Input LRCK and Output LRCK. 
 Input port  →  Output port 
 I2S              →  LSBJ/MSBJ :  1.5/fs 
 I2S              →  I2S              :  1.0/fs 
 LSBJ/MSBJ   →  LSBJ/MSBJ :  1.0/fs 
 LSBJ/MSBJ   →  I2S               :  0.5/fs 
 However, there are variations about 1/fs.
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[Q0073]
・When the AK4129 converts 24-bit input to 16-bit output, how is the remaining LSB 8 bits processed?
A.
・The SRC block is processed with 24-bit data. However, when 16-bit output setting is selected, the result of SRC is rounded into 16-bit and output, with dither added to the LSB if dither is enabled.
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[Q0074]
・Is the following conversion possible with the AK4129? 
TDM data input (fsi=192/96kHz) → TDM data output (fso=48kHz)
A.
・The AK4129 supports TDM mode, but does not support fs 192KHz and 96KHz. The maximum sample rate is up to 48kHz in TDM mode for both input and output ports.
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[Q0075]
・Is the following conversion possible with the AK4129? 
2x asynchronous TDM data input (fsi=48kHz) → TDM data output (fso=96kHz)
A.
・The AK4129 does not support two asynchronous TDM input sources. The sample rate at the output port is also out of spec.
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[Q0076]
・Is the following conversion possible with the AK4129? 
TDM data input (fsi=48kHz) + I2S 2ch data input (fsi=48kHz) (Input sources are asynchronous) → TDM data output (fso=96kHz)
A.
・The AK4129 does not support TDM and I2S at the same time on the same port. The sample rate at the output port is also out of spec.
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[Q0077]
・Is the following conversion possible with the AK4129? 
3 x I2S data input (fs=48kHz) → TDM data output (fs=192 kHz)
A.
・The AK4129 does not support 192kHz in TDM format on the output port. The output port supports TDM format up to fso = 48kHz. Three streams of I2S format data on the input port are available in both synchronous and asynchronous mode.
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[Q0078]
・The AK4129 supports 32-bit BICK/data slot in TDM format in the specifications. Is 24-bit BICK/data slot supported in TDM mode?
A.
・The AK4129 supports only 32-bit BICK/data slot in TDM mode.
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[Q0079]
・The datasheet says "it should be reset by the PDN pin or RSTN bit in serial control mode" when external clock is changed. Without PDN pin/RSTN bit setting, what happens with the output of the AK4129?
A.
・The AK4129 may generate pop noise when the external clock is changed without PDN pin/RSTN bit setting. An alternative way to avoid pop noise is to put the AK4129 into mute state when changing clocks.
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[Q0080]
・When using a single AK4128A for an 8ch input system and operating it in synchronous mode, is there any phase shift on 8 channels?
A.
・There is no phase shift on 8 channels.
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[Q0081]
・When using two of AK4128A's for a 16ch input system and operating them at the same time in synchronous mode, is there any phase shift between two AK4128A's (16ch output)?
A.
・The SRC block of the AK4128A is operated by built-in OSC. Even if the external clocks (IBICK, ILRCK, OBICK, OLRCK) are the same on the two AK4128A's, the conversion timing will not be exactly the same because each device has a free-running clock that influences the conversion timing. 
This means there may be some small signal phase shift reflected in the SRC output data.
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