FAQ

AFE with A/D Converter

AK924X

[Q0113]
・Is it possible to read normal output data simultaneously in polar coordinate output mode?
A.
・No, it is not possible.  In polar coordinate output mode, "angle" and "moving radius" data is output, and data of normal output mode cannot be output.  It will be in the same manner in normal output mode.
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[Q0114]
・How is it calculated in polar coordinate output mode?
A.
・It is calculated by CORDIC (Coordinate Rotation Digital Computer).  CORDIC is an algorithm for finding mathematical functions like trigonometric function by only adding and subtracting.
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[Q0115]
・Tell me about the structure of current input circuit.
A.
・It is composed by a transimpedance amplifier.  Please refer to “Current Input Mode” paragraph of functional descriptions in datasheet.
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[Q0116]
・Once you write a register setting, will it be automatically reflected on reboot after stopping the power supply?
A.
・No, it will not be reflected automatically.  Make sure to write desired registers upon power-up or after reset.
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[Q0117]
・Is it possible to connect the register WRITE pin and READ pin to the I/O port together?
A.
・Yes, it is possible.
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[Q0118]
・Is it possible to adjust offset, gain, and phase for each sampling?
A.
・Yes, it is possible.  They can be adjusted by updating each register value by SPI communication.  Since it is a register setting, it is also possible to change the correction amount at an arbitrary timing.
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[Q0119]
・Are offset, gain and phase correction are executed automatically?
A.
・No, they are not.  It is necessary to write an arbitrary setting value to the register.
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[Q0120]
・Is there any way to reduce current consumption?
A.
・Yes.  Please refer to 【Application Notes】 for details.
Click here for details
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[Q0121]
・Can CSN and SCLK be used asynchronously?
A.
・No, it is not possible.  These signals must be used in synchronous operation.
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[Q0122]
・Are both High and Low states of SCLK accepted at CSN Low edge?
A.
・It depends on the product.
<AK9242NK>
 No.  In the case of the timing shown below, MSB data will not be output if SCLK is Low on the falling edge of CSN.  Therefore, the SCLK signal must be High on the falling edge of CSN.
<AK9240NK> Yes, both states are accepted.
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[Q0123]
・Is SCLK input necessary during High period of CSN?
A.
・No, it is not necessary.  However, SCLK state must be set according to the question [Q0122].
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[Q0124]
・Is there any way to reduce digital wiring?
A.
・Yes, there are various methods depending on the products.  Please refer to 【Application Notes】 for details.
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