FAQ - 音频数模转换器

上电后,Power down解除的顺序是什么?

[Q0022]

回答

上电后,请将PDN pin: “L” →”H”。请注意保证PDN pin Low区间>Reset 区间 (tPD) 。

启动后时钟输入Timing是什么?

[Q0023]

回答

如果是在上电后供给时钟的话,时钟的Timing并没有限制。如果是Power up之后供给时钟的话,时钟供给之后内部回路才开始工作,随后模拟电路Power up。

具有时钟Power down功能的IC,如果停止供给MCLK和LRCK,IC处于Power down状态下,模拟输出管脚会是什么状态?

[Q0024]

回答

模拟输出管脚输出Hi-Z。

具有时钟Power down功能的芯片,如果处于Power down状态下,寄存器值会被初始化吗?

[Q0025]

回答

寄存器值不会被初始化。

TDM256Mode,fs44.1kHz时,需要供给主钟频率多少?

[Q0026]

回答

需要供给11.2896MHz (256fs) 以上的主钟频率。详细请参考各个芯片的数据手册。

数字输入信号有上过冲和下过冲限制吗?

[Q0027]

回答

没有。但是如果输入信号超过了数据手册中记载的最大定额电压VIND的值,芯片会受损,不能保证正常工作。

输入端数字管脚的输入电容是多少?

[Q0028]

回答

输入电容在5pF以下。

如何处理未使用的模拟输出管脚?

[Q0029]

回答

断开 (Open) 状态。

模拟输出管脚的输出电阻是多少?

[Q0030]

回答

没有输出电阻指标。但实际值一般在1Ω以下。

连接VCOM管脚的电容过小的话会有什么优缺点?

[Q0031]

回答

容量小的话
优点: VCOM的启动时间短,很快能进入工作状态。
缺点: 1. 受噪声的影响大。
2. 会出现上电噪声。

VCOM管脚电压安定前输入数字信号的话,模拟输出信号会出现什么问题?

[Q0032]

回答

模拟输出信号会出现失真。

模拟特性中阻抗负荷电阻,是在输入信号fin 1kHz的定义吗?

[Q0033]

回答

是输入信号频率在20Hz~20kHz范围内的定义。主要定义的是最后段Amp可以驱动的负载。

DAC模拟输出端口可以输出DC电压吗?

[Q0034]

回答

DAC输出规格中没有定义DC电压。输出范围的定义在20Hz~20kHz。

请提供差分输出转换成单端输出的外部模拟电路以及频率计算式。

[Q0035]

回答

以AK4482为例。在数据手册中的模拟输出部分以及测试板手册中记载了外部模拟滤波器电路和LPF的计算。

Group Delay (群延迟) 的定义是什么??为什么没有Min/Max值?

[Q0036]

回答

Group Delay (群延迟) 是指从初始化音频I/F数据开始到模拟信号输出为止芯片内部处理需要的时间。主要是芯片内部数字滤波器引起的延迟,所以基本上没有变动。

有复数输入通道时,各通道之间是否存在相位差?

[Q0037]

回答

各通道之间不存在相位差。

Power down解除后 (PDN pin: L→H),读写寄存器需要多长等待时间?

[Q0038]

回答

Power down解除后立刻可以读写寄存器,不需要等待时间。

假如HOST在通信中将CSN pin设置为 “H”强制中断通信,那么之前写进的数据会如何为变化?

[Q0039]

回答

通信中将CSN pin从”L”→”H”,寄存器值不会被更新。

请提供Mono-Mode设定时,寄存器配置和外部Post Filter。

[Q0040]

回答

以AK4490为例,请参考如下电路原理图。

FAQ - 音频数模转换器

Audio D/A Converters

[Q0022]
・Tell me power-down release (power up) sequence after tuning power supplies on.
A.
・Turn power supplies on while the PDN pin = "L" and then set the PDN pin to "H" after Reset period (tPD) is passed.
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[Q0023]
・Tell me clock input timing at start-up.
A.
・A clock can be input anytime after power supplies are turned on. However, if the clock is input after releasing power-down, internal circuit timing starts by a clock input and then the analog block is powered up.
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[Q0024]
・If the device supports clock power-down mode, what is the analog output pin's status in power-down mode when MCLK and LRCK are stopped?
A.
・The analog out pins are in Hi-Z state.
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[Q0025]
・If the device supports clock power-down, will register settings be cleared and become default value by clock power-down?
A.
・Register settings will not be initialized by clock power down.
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[Q0026]
・What should be the master clock frequency when using TDM256 mode with 44.1kHz sampling frequency?
A.
・Input a master clock that is equal or faster than 11.2896MHz (256fs). Please refer to the datasheet of each device in detail.
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[Q0027]
・Are there any specifications of overshoot and undershoot in the digital input signal?
A.
・Overshoot and undershoot of digital inputs are not specified. Operation beyond VIND limits may result in permanent damage to the device. Normal operation is not guaranteed at this extreme.
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[Q0028]
・How much capacitance does the digital input pin have?
A.
・The input capacitance will be less than 5pF.
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[Q0029]
・How should the unused analog output pins be handled?
A.
・They should be handled as open.
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[Q0030]
・What is the output resistance value of the analog output pin?
A.
・Output resistance value is not being specified and guaranteed. It will be 1Ω or less as the actual value.
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[Q0031]
・What are advantages and disadvantages when the capacitance connected to the VCOM pin becomes smaller?
A.
・Advantage: The startup time is faster than normal.
 Disadvantage:
 1 - It is more susceptible to noise influence. SNR performance may be degraded.
 2 - Transient of "pop" noise shall be increased upon power up.
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[Q0032]
・What happens to the analog output if digital data is input before the the VCOM voltage is stable?
A.
・Please note that the analog output waveform may be distorted if digital data in input before the VCOM voltage is stable.
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[Q0033]
・Regarding the Load Resistance of dac what input frequency do this product specify? The condition of input frequency is only 1kHz?
A.
・Input signal frequency is specified from 20Hz to 20kHz. It obtains a load that can drive an amplifier at the following stage.
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[Q0034]
・Does the DAC generate stable DC output ?
A.
・The DAC can generate a DC output. However, there are no tested and guaranteed performance/accuracy specs below the range of 20Hz to 20kHz.
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[Q0035]
・Do you have a circuit diagram of external analog filter that converts differential output to single-ended signal and the calculation formula of frequency characteristics?
A.
・The circuit diagram of external analog filter and LPF calculation formula are written in Analog Output of the datasheet and the evaluation board manual. (example AK4482)
fig
External Analog Filter Circuit
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[Q0036]
・What is the definition of Group Delay? Is there any reason for that they don't have min/max values?
A.
・The definition of the group delay is the time from data coming in the device to data output to the device at their respective pins. This usually shows in number of 1/fs unit.This is mainly caused by the taps of the digital filter. Therefore there are no variations.
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[Q0037]
・Is there phase difference between channels if the device has multiple input channels?
A.
・There is no phase difference between channels.
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[Q0038]
・Is a wait time necessary to start accessing to registers after releasing power-down (PDN pin: "L"→ "H") ?
A.
・A wait time is not necessary since register access is available after power-down is released.
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[Q0039]
・What happens to written data if the data communication from HOST is cut forcibly by setting the CSN pin to "H" ?
A.
・Written commands are cancelled and registers are not updated if the CSN pin is set to "H" from "L" during a communication.
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[Q0040]
・Do you have the register setting and the external post circuit block in the mono mode?
A.
・A circuit schematic diagram is shown here (AK4490).
fig
AK4490 External Circuit Example
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VELVET SOUND