FAQ - Audio DACs

전원투입 후, Power Down 해제의 Sequence를 알려주세요.

[Q0022]

Answer

전원투입 후, PDN핀을 L ⇒ H로 해 주세요.. 이 경우 Low상태를 최저 Reset 시간(tPD) 이상 유지 해 주세요.

기동 시의 Clock입력의 Timing 알려 주세요.

[Q0023]

Answer

전원이 투입된 후라면 어느 Timing에서도 Clock 입력은 가능합니다. 단, Power Down해 제 후에 Clock을 공급했을 때는  Clock이 공급이 되고 나서 내부회로의 Timing이 Start하고, Analog BLock이 Power Up 합니다.

Clock Power Down을 지원하고 있는 Device에서 MCLK 및 LRCK의 공급이 멈춰 Power Down상태가 된 경우, Analog 출력 Pin의 상태는 어떻게 됩니까?

[Q0024]

Answer

Analog 출력 Pin은 Hi-z가 됩니다.

Clock Power Down을 지원하고 있는 Device에서 Power Down 후에 Register 설정값은 Clear되어 Default값이 되나요?

[Q0025]

Answer

11.2896MHz (256fs) 이상의 Master Clock 입력하십시오. 자세한 내용은 개별 Device의 Data Sheet를 참조 해 주세요.

TDM256 모드를 사용하는 경우, fs44.1kHz일 때 Master Clock은 몇 MHz를 공급하면 됩니까?

[Q0026]

Answer

전원투입 후, PDN핀을 L ⇒ H로 해 주세요.. 이 경우 Low상태를 최저 Reset 시간(tPD) 이상 유지 해 주세요.

Digital 입력 신호의 Overshoot, Undershoot의 Sped은 있나요?

[Q0027]

Answer

Spec은 없습니다. Datasheet의 절대최대정격 VIND의 값을 초과한 조건에서 사용한 경우, Device가 파손 될 수 있습니다. 또한, 통상의 동작은 보증하지 않습니다.

Digital 입력 pin의 입력 용량은 어느정도 입니까?

[Q0028]

Answer

입력 용량은 5pF 이하 입니다.

사용하지 않는 Analog 출력 Pin의 처리는 어떻게 하면 됩니까?

[Q0029]

Answer

Open으로 해주세요.

Analog 출력 Pin의 출력 저항값은 어느정도 입니까?

[Q0030]

Answer

출력 저항값은 Spec, 보증은 하지 않습니다.  실력치로써 1Ω이하로 생각 해 주세요.

VCOM Pin에 접속하는 Condenser 용량을 작게 했을 경우의 장점, 단점을 알려주세요.

[Q0031]

Answer

용량을 작게 할 경우
장점 : VCOM Start Up 시간이 단축되고, 동작 상태가 빨라 집니다.
단점 : 1. noise 영향을 쉽게 받게 됩니다.
2. 전원 투입시 Pop Noise가 출력됩니다.

VCOM 핀의 전압이 안정되기 전에 Digtal Data를 입력하게 되면 출력은 어떻게 됩니까?

[Q0032]

Answer

VCOM Pin의 전압이 안정되기 전에 Digital Data가 입력 된 경우, Analog 파형이 왜곡 될 수 있으므로 주의가 필요합니다.

Alanog 특성의 부하 저항 (Load Resistance)의 스펙은 입력 신호의 주파수가 fin 1KHz일 때만 입니까?

[Q0033]

Answer

입력신호 주파수의 사양은 20Hz ~ 20KHz 입니다. 최종 단의 Amp가 구동할 수 있는 부하입니다.

DAC의 Analog 출력 단자에서 DC 출력은 가능합니까?

[Q0034]

Answer

DC 출력은 Spec화 하지 않습니다.  Data sheet 상의 측정대역은 20Hz~20kHz입니다.

차동 출력을 Single End로 변환하는 외부 Analog Filter 회로와 그 주파수 특성의 계산식을 알려주세요.

[Q0035]

Answer

AK4482로 예를 들어보겠습니다. 외부 Analog Filter 회로도, LPF의 계산식은 Datasheet의 Analog 출력 및 평가보드 매뉴얼에 기재되어 있습니다.

Group Delay의 정의를 알려주세요. 또한 min/Max 값이 없는 이유를 알려주세요.

[Q0036]

Answer

정의는 Audio I/F에 Data가 Set 되고나서 부터 Analog 출력 Pin에서 출력 될 때까지의 내부처리 시간입니다. 주로 내부 Digital Filter에 의한 지연이므로 편차는 없습니다.

입력 Channel가 복수인 경우, Channel 간에 위상 차이는 있습니까?

[Q0037]

Answer

Channel 간에 위상 차이는 없습니다.

Power Down 해제 (PDN pin : L→H) 후, Register Access를 함에 있어서  대기 시간을 넣을 필요가 있습니까?

[Q0038]

Answer

Power Down 해제 후 Register Acces가 가능하기 때문에 대기 시간을 넣을 필요는 없습니다.

HOST에서 통신중에 CSN을 강제로 H로 해서 Data 통신을 중단한 경우, 그때 까지 Writing 한 Data 어떻게 됩니까?

[Q0039]

Answer

HOST에서 통신중에 CSN pin을 L → H로 한 경우, Command는 Cancel되어 Register는 갱신되지 않습니다.

Mono Mode로 설정한 경우의 Register 설정과 외부 Post Filter를 알려주세요.

[Q0040]

Answer

AK4490의 회로 모식도 예는 여기를 참조해주세요.

FAQ - Audio DACs

Audio D/A Converters

[Q0022]
・Tell me power-down release (power up) sequence after tuning power supplies on.
A.
・Turn power supplies on while the PDN pin = "L" and then set the PDN pin to "H" after Reset period (tPD) is passed.
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[Q0023]
・Tell me clock input timing at start-up.
A.
・A clock can be input anytime after power supplies are turned on. However, if the clock is input after releasing power-down, internal circuit timing starts by a clock input and then the analog block is powered up.
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[Q0024]
・If the device supports clock power-down mode, what is the analog output pin's status in power-down mode when MCLK and LRCK are stopped?
A.
・The analog out pins are in Hi-Z state.
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[Q0025]
・If the device supports clock power-down, will register settings be cleared and become default value by clock power-down?
A.
・Register settings will not be initialized by clock power down.
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[Q0026]
・What should be the master clock frequency when using TDM256 mode with 44.1kHz sampling frequency?
A.
・Input a master clock that is equal or faster than 11.2896MHz (256fs). Please refer to the datasheet of each device in detail.
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[Q0027]
・Are there any specifications of overshoot and undershoot in the digital input signal?
A.
・Overshoot and undershoot of digital inputs are not specified. Operation beyond VIND limits may result in permanent damage to the device. Normal operation is not guaranteed at this extreme.
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[Q0028]
・How much capacitance does the digital input pin have?
A.
・The input capacitance will be less than 5pF.
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[Q0029]
・How should the unused analog output pins be handled?
A.
・They should be handled as open.
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[Q0030]
・What is the output resistance value of the analog output pin?
A.
・Output resistance value is not being specified and guaranteed. It will be 1Ω or less as the actual value.
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[Q0031]
・What are advantages and disadvantages when the capacitance connected to the VCOM pin becomes smaller?
A.
・Advantage: The startup time is faster than normal.
 Disadvantage:
 1 - It is more susceptible to noise influence. SNR performance may be degraded.
 2 - Transient of "pop" noise shall be increased upon power up.
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[Q0032]
・What happens to the analog output if digital data is input before the the VCOM voltage is stable?
A.
・Please note that the analog output waveform may be distorted if digital data in input before the VCOM voltage is stable.
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[Q0033]
・Regarding the Load Resistance of dac what input frequency do this product specify? The condition of input frequency is only 1kHz?
A.
・Input signal frequency is specified from 20Hz to 20kHz. It obtains a load that can drive an amplifier at the following stage.
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[Q0034]
・Does the DAC generate stable DC output ?
A.
・The DAC can generate a DC output. However, there are no tested and guaranteed performance/accuracy specs below the range of 20Hz to 20kHz.
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[Q0035]
・Do you have a circuit diagram of external analog filter that converts differential output to single-ended signal and the calculation formula of frequency characteristics?
A.
・The circuit diagram of external analog filter and LPF calculation formula are written in Analog Output of the datasheet and the evaluation board manual. (example AK4482)
fig
External Analog Filter Circuit
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[Q0036]
・What is the definition of Group Delay? Is there any reason for that they don't have min/max values?
A.
・The definition of the group delay is the time from data coming in the device to data output to the device at their respective pins. This usually shows in number of 1/fs unit.This is mainly caused by the taps of the digital filter. Therefore there are no variations.
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[Q0037]
・Is there phase difference between channels if the device has multiple input channels?
A.
・There is no phase difference between channels.
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[Q0038]
・Is a wait time necessary to start accessing to registers after releasing power-down (PDN pin: "L"→ "H") ?
A.
・A wait time is not necessary since register access is available after power-down is released.
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[Q0039]
・What happens to written data if the data communication from HOST is cut forcibly by setting the CSN pin to "H" ?
A.
・Written commands are cancelled and registers are not updated if the CSN pin is set to "H" from "L" during a communication.
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[Q0040]
・Do you have the register setting and the external post circuit block in the mono mode?
A.
・A circuit schematic diagram is shown here (AK4490).
fig
AK4490 External Circuit Example
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