FAQ - 音频模数变换器

在Power-down期间,时钟输入和数据输出引脚是什么状态?

[Q0041]

回答

时钟引脚为Hi-Z,数据输出引脚为低电平。

PDN引脚是否有特定的上升时间规定?

[Q0042]

回答

PDN引脚的上升时间并没有特殊规定。

Power-down的解除,是通过检测PDN引脚的电平 (高/低),还是边缘捕获?

[Q0043]

回答

Power-down的解除,是由PDN引脚高电平和主时钟 (MCLK) 输入后的LRCK时钟的边缘决定的。

Power-down的时序是什么?

[Q0044]

回答

Power-down (PDN引脚=H→L) 以后,停止输入时钟。有些芯片具有通过停止时钟来自动实现Power-down的功能。详细请参考各芯片数据手册。

数据手册中描述上电后,PDN引脚要从 "H "状态变为 "L "状态,再变回 "H "状态。
那么如果上电后控制PDN引脚保持 "L "状态,然后再变为 "H "状态,是否会有问题?

[Q0045]

回答

没有问题。上电后,将PDN引脚由 "L "变为 "H"。请注意保持低电平状态的时间至少为最小复位时间 (tPD)。

什么时候可以输入外部时钟输入?

[Q0046]

回答

只要是上电后,无论是否解除Power-down,都可以输入时钟。

时钟输入的顺序是否有限制?

[Q0047]

回答

时钟输入的顺序没有限制。

数据手册中描述的,"主时钟 (MCLK) 和通道时钟 (LRCK) 需要同步,但不需要对准相位 "是什么意思?

[Q0048]

回答

是指由于MCLK和LRCK是从同一时钟源分压产生的,所以相位差并不是问题。

外部输入时钟的上升和下降时间是否有限制?

[Q0049]

回答

没有限制。但请使用单调增减的时钟,包括高频噪音。

当主时钟出现抖动时,音质会受到影响。但如果LRCK和BICK也同样出现时钟抖动时,音质也会受到影响吗?

[Q0050]

回答

Δ-Σ调制器的工作是基于主时钟的。由于通道时钟 (LRCK) 和串行数据时钟 (BICK) 只用于芯片内部数据输入/输出和锁存,所以LRCK和BICK出现抖动一般也不会影响音质。

该如何处理未使用的模拟输入引脚?

[Q0051]

回答

这取决于输入形态。单端输入时应保持开放。差分输入时,输入+和输入-引脚有可能是开路的,或者+和-引脚短路开路,或者连接到GND。详细请参考各芯片数据手册。

数字输入引脚的输入容量是多少?

[Q0052]

回答

输入容量小于5pF。

数字输入引脚是否有上拉/下拉 (Pull up / down) 电阻?

[Q0053]

回答

如果有上拉/下拉电阻,数据手册中会有明确标记。

ADC输出中的直流偏移是什么原因造成的?

[Q0054]

回答

如果关闭ADC的输入HPF,有可能产生直流偏移。

请告知在使用通道加法模式时,外部模拟输入缓冲电路例。

[Q0055]

回答

请参考电路例。

差分输入的ADC中,输入电压+/-2.8Vpp的含义是什么?

[Q0056]

回答

+/-2.8Vpp规格单位的含义是:AINxP引脚 (任意差分输入对的输入端) 的交流信号电压部分的摆幅电平为2.8Vpp,而AINxN引脚的摆动相位相反,即为-2.8Vpp。

在实际应用中,差分对的摆幅为AINxP-AINxN=5.6Vpp。请注意,这只是驱动ADC到满量程时信号摆动的交流部分,电压值并没有以地为基准。所以实际信号还应包含一个直流偏置电压。

外部提供的直流偏置电压应设置为模拟电源电压的大约1/2。

单端输入ADC中,输入电压2.8Vpp的含义是什么?

[Q0057]

回答

2.8Vpp是指AINx引脚 (任意一个单端通道的输入端) 摆动交流信号的摆幅是2.8 Vpp。请注意,这只是驱动ADC到满量程时信号摆动的交流部分,电压值并没有以地为基准。

所以实际信号需要包含一个直流偏置电压。VCOM=(模拟电源电压/2)VDC是通过电容耦合,由内部自偏压电路来提供。

差分输入的ADC,能否对差分输入信号进行AC耦合?

[Q0058]

回答

除AK5730,AK5522和AK5703外,不允许使用交流耦合输入。高性能差分输入芯片一般需要严格匹配OP-Amp电路与输入端采样和保持电路。

这些输入不包含任何集成的自偏压电路。外部偏置虽然可能使用,但很可能导致性能下降,特别是THD+N。

在差分输入ADC产品中,如果外部信号只输入给AINxP引脚,而没有输入给AINxN引脚,会发生什么情况?

[Q0059]

回答

芯片要正常工作,必须同时向差分输入AINxP引脚输入信号,并向AINxN引脚输入相位相反的信号。

如果只驱动差分对输入信号的一侧,会导致电平下降6dBFS,失真特性降低。

在数据手册中,开机/关机顺序中有叫 "Idle Noise "的噪声,这是什么噪声?

[Q0060]

回答

Idle Noise是指在ADC正常运行时,没有输入信号时的数字输出。与S/N规格的输出相同。

在Power-down状态下访问寄存器是否有效?

[Q0061]

回答

在Power-down状态下 (PDN=”L”),寄存器访问是无效的。只有在Power-down解除后才可以访问寄存器。

有些芯片在音频时钟停止时是不允许访问寄存器的。各芯片的寄存器访问条件请参考各数据手册。

FAQ - 音频模数变换器

Audio A/D Converters

[Q0041]
・What are the clock input pin and the data output pin statuses in power-down mode?
A.
・The clock input pins are in Hi-z status. The data output pins are in Low level.
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[Q0042]
・Is there any restriction about PDN rising time?
A.
・There is no restriction about PDN rising time.
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[Q0043]
・Which action does execute power-down release: PDN pin level (H/L) detection or clcok edge input?
A.
・Power-down is released by MCLK and LRCK edges after the PDN pin is set to "H."
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[Q0044]
・What is the power-down sequence?
A.
・Stopping the clocks after setting the PDN pin = "H" → "L" is preferred. However, if the audio clocks are stopped first the device will enter power-down mode automatically for almost all recent generation devices. Please refer to the datasheet of each device in detail.
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[Q0045]
・Is there any problem if the PDN pin is kept to "L" when power supplies are On and then it is set to "H"? 
In the datasheet, it could be understood as that the PDN pin should be set to "L" first and set to "H" (H→L→H) after power supplies are on.
A.
・No Problem. Turn power supplies on while the PDN pin = "L" and then set the PDN pin to "H" after Reset period (tPD) is passed.
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[Q0046]
・When is the appropriate timing to input external clocks?
A.
・If the power supplies are On, external clocks can be input at any timing regardless of power-down release.
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[Q0047]
・Do I have to care about the input order of clocks?
A.
・There is no restriction about the input order of clocks.
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[Q0048]
・What does the expression "The LRCK clock input must be synchronized with MCLK, however the phase is not critical." in the datasheet mean substantially?
A.
・MCLK and LRCK should be generated by dividing the same clock source. The phase difference will not matter in this case.
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[Q0049]
・Is there any restriction about the rise/fall time of external input clock?
A.
・There is no timing restriction about the external clock input. However, the input clock swing must transit monotonically without including higher frequency noise.
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[Q0050]
・Does clock jitter on LRCK or BICK affect sound quality as well as clock jitter on MCLK?
A.
・The internal delta-sigma modulator operates on MCLK. LRCK and BICK are only used for latching input/output data, therefore generally clock jitter on LRCK or BICK does not affect the sound quality.
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[Q0051]
・How should the unused analog input pins be handled?
A.
・Handling may differ depending upon the specific ADC device. Single-ended input devices should normally be left open to allow the pin(s) to stabilize at their self-biasing point.
 Differential input devices should have their input+ and input- pins shorted together and the pair either grounded or left floating.
Each device should have specific recommendations in their respective datasheet Handling of Unused Pins section.
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[Q0052]
・How much capacitance does the digital input pin have?
A.
・The input capacitance will be less than 5pF.
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[Q0053]
・Does the digital input pin have internal pull up/down resistor?
A.
・The handling varies case-by-case of specific pins and specific devices. It will be specified in the datasheet if they have internal pull up/down resistors.
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[Q0054]
・DC offset is added to the AD output. What is it caused by?
A.
・Residual DC offset does occur by the conversion process and shall be evident if the digital HPF is disabled. In most cases enabling the HPF is a very satisfactory solution to eliminating this offset.
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[Q0055]
・Do you have a circuit diagram example of external analog input buffer circuit for channel summation mode?
A.
・Please refer to  the example of circuit diagram.
Click here for details
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[Q0056]
・Explain the Input Voltage specs (differential input device). For example, how are the units +/-2.8Vpp to be interpreted?
A.
・The meaning of +/-2.8Vpp spec units is the AINxP pin (plus input of any channel's differential input pair) is to swing its AC signal voltage portion at the level of 2.8Vpp, while the AINxN pin is to swing opposite phase and stated as -2.8Vpp. It is actually most conventionally correct to state this voltage as AINxP - AINxN = 5.6Vpp total swing of the differential pair. Notice that however stated this is only the AC portion of the signal swing relative to driving the ADC to full-scale and the voltage values are not referenced to ground. 
It is assumed that the proper signal conditions are to include the DC bias voltage of approx. VCOM = ~ (AVDD/2) which is to be also provided by the external buffer circuit.
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[Q0057]
・Explain the Input Voltage specs (single-ended input device). For example, how are the units 2.8Vpp to be interpreted?
A.
・The meaning of 2.8Vpp units the AINx pin (input of any channel) is to swing its AC signal voltage portion at the level of 2.8Vpp. Notice that this is only the AC portion of the signal swing relative to driving the ADC to full-scale and the voltage value is not referenced to ground. It is assumed that the proper signal conditions are to include the DC bias voltage of approx. VCOM = ~ (AVDD/2) which shall be provided internally by the self-biasing circuit while the signal is coupled via capacitor.
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[Q0058]
・Can I AC couple the input signal (differential input device)?
A.
・Generally, no, except the AK5730, AK5522 or AK5703 devices. High performance differential input devices require critical matching of the driving Op-amp circuit to the input's internal Sample and Hold circuit. The inputs do not contain any integrated self-biasing circuitry. Passive external biasing, while maybe possible, is likely to cause degraded performance, particularly THD+N.
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[Q0059]
・Can I drive only the AINxP input signal single-ended, while not driving AINxN (differential input device)?
A.
・Normal swing of both the AINxP input while the AINxN input is driven with opposite phase is necessary to properly drive the device to full-scale. Driving only one input signal of the differential pair will result in only -6dBFS level until abnormal distortion will occur as the level is attempted to be increased.
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[Q0060]
・What kind of noise is Idle Noise? It is written in the power on/off sequence of the datasheet for ADC.
A.
・Idle Noise is a digital output without input signal in normal ADC operation. It is the same output as the S/N specification.
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[Q0061]
・Is a register access valid in power-down mode?
A.
・Register access is not valid if PDN is LOW. However, certain devices do allow register access while the audio clocks are stopped and the device is in power-down mode automatically. Conditions for when register access is not allowed specific to each device are specified in notes at the bottom of the first page of the Register Control Interface section in the datasheet.
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