FAQ - Audio ADCs

Power Down시의 Clock 입력 pin, Data 출력pin의  단자 상태는 어떻게 됩니까?

[Q0041]

Answer

Clock pin은 Hi-Z가 됩니다. Data 출력 pin은 Low Level이 됩니다.

PDN Pin의 기동 시간 규정이 있습니까?

[Q0042]

Answer

PDN Pin의 기동 시간 규정은 없습니다.

Power Down 해제는 PDN 핀의 Level (Hi/Low) 검출입니까? Edge Detection 입니까?

[Q0043]

Answer

Power Down 해제는 PDN pin 이 High가 되고, Master Clock (MCLK) 입력 후의 Channel Clock (LRCK)의 Edge로  확정됩니다.

Power Down으로 하기 위한 Sequence를 알려주세요.

[Q0044]

Answer

Pin Power Down(PDN pin = H → L)을 하고나서 Clock을 정지 해 주세요. 또한 최신 Device중에는 Clock 정지에 의한 Power Down 기능을 가지고 있는 것도 있습니다. 자세한 내용은 Datasheet 참조하십시오.

전원 투입 후, PDN pin을 H상태에서 한 번  L로 하고나서 H로 한다라는 표현이 있습니다만, 전원 투입 후 PDN pin L을 유지한 상태에서 H로하는 제어에서도  문제 없습니까?

[Q0045]

Answer

문제는 없습니다. 전원 투입 후, PDN 핀을 L⇒H로 해 주십시오. 이 경우 Low 상태를 최저 Rest 시간 (tPD) 이상 유지해 주십시오.

외부 Clock을 입력하는 Timing에 제약이 있습니까?

[Q0046]

Answer

전원 투입 후라면 Power Down  해제 전후와 관계없이 Clock 입력은 가능합니다.

Clock 입력 순서에 제약은 있습니까?

[Q0047]

Answer

Clock 입력 순서에 제약은 없습니다.

Datasheet에 기재된 "Master Clock (MCLK) 과 Channel Clock (LRCK)은 동기화 할 필요가 있지만, 위상을 맞출 필요는 없습니다." 는 구체적으로 무엇을 의미합니까?

[Q0048]

Answer

MCLK와 LRCK는 동일 Clock Source에서 분주하여 생성해 주십시오. 그 때의 위상차는 문제가 되지 않습니다.

외부입력 Clock의 Rising/Falling 시간의 규정이 있습니까?

[Q0049]

Answer

규정은 없습니다. 단, 고주파 Noise를 포함해서 단조(単調) 증가, 감소하는 Clock입력해주십시오.

Master Clock에 Jitter가 타고 있는 경우에는 음질에 영향을 준다고 생각합니다만, LRCK, BICK에 동일한 Clock Jitter가 타고 있는 경우, 일반적으로 음질에 영향이 있습니까?

[Q0050]

Answer

ΔΣ Modulator의 동작은 Master Clock 기준으로 동작합니다. Device 내부에서 Channel Clock (LRCK), Serial Data Clock (BICK)은 Data 입출력,  latch에 사용 되었을 뿐이므로 일반적으로 음질에 영향을 줄 수는 없습니다.

사용하지 않는 Analog 입력 pin의 처리는 어떻게 하면 됩니까?

[Q0051]

Answer

입력 형식에 따라 다릅니다. Single Ended 입력 Type는 Open으로 해주십시오. 차동 입력 Type는 Input +pin과 Input -pin을 Open의 경우와, 이 +pin과 -pin을 Short해서 Open 또는 GND에 연결하는 경우가 있습니다.

자세한 내용은 개별 Device의 Datasheet를 참조해주십시오.

Digital 입력 pin의 입력 용량은 어느 정도 입니까?

[Q0052]

Answer

입력 용량은 5pF 이하 입니다.

Digital 입력 pin에 Pull Up/Down 저항은 붙어 있나요?

[Q0053]

Answer

Pull Up/Down 저항이 붙어 있는 경우는 표기되어 있습니다.

ADC 출력에 DC Offset이 타고 있습니다만,, 원인이 무엇인지 알 수 있습니까?

[Q0054]

Answer

ADC 입력 HPF가 OFF로 되어있지 않는지 확인해 주십시오.

Channel 가산 Mode를  사용할 경우, 외부 Analog 입력 Buffer 회로 예를 알려주십시오.

[Q0055]

Answer

회로 예를 참조해 주십시오.

차동입력 ADC 제품에서 입력 전압 (Input Voltage) 의 의미를 알려 주십시오.

[Q0056]

Answer

+2.8Vpp 사양 단위의 의미는 AINxP pin (임의의 차동 입력 Pair의 입력)은 AC 신호 전압 부분을 2.8Vpp Level에서 Swing t시키는 것이며, AINxN  pin은 역위상으로 Swing하고 이때 -2.8Vpp가 됩니다.

실제로는 이 전압을 차동 Pair의 AINxP-AINxN = 5.6Vpp Total Swing으로 표현하는 것이 가장 적합합니다.

그러나 이것은 ADC를 Full Scale로 구동하는 경우의 신호 Swing의 AC부분 만이며 전압값은 Ground을 기준으로 하고 있지 않다는 것에 유의하십시오.

적절한 신호 조건에는 약간의 DC  Bias 전압이 포함되어 있는 것으로 합니다. 외부에서 공급하는 DC  Bias 전압은 대략 Analog 전원의 1/2로 설정하십시오.

Single ended 입력 ADC 제품에서 입력 전압 (Input Voltage) 의 의미를 알려주십시오.

[Q0057]

Answer

2.8Vpp 단위의 의미는 AINxP 핀 (임의의 Single ended Channel의 입력)은 AC 신호전압 부분을 2.8Vpp Level에서 Swing하는 것입니다.

이것은 ADC를 Full Scale로 구동하는 경우의 신호 Swing의 AC 부분 만이며, 전압 값은 Ground 기준으로 하고 있지 않다는 것을 유의 해 주세요.

적절한 신호 조건에는 약간의  DC Bias  전압이 포함되어 있는 것으로 합니다.

VCOM=대략 (Analog전원/2) VDC는 신호가 Condenser를 매개로 Coupling 되어있는 동안 자기 bias 회로에 의해 내부적으로 공급됩니다.

차동 입력 ADC 제품에서 차동 입력을 AC 결합 가능한가요?

[Q0058]

Answer

AK5730, AK5522 또는 AK5703 Device를 제외하고 AC 결합 입력은 불가능합니다.

일반적으로 고성능 차동 입력 Device는 OP-Amp 회로와 입력 내부 Sample & Hold 회로의 중요한 Maching 을 필요로 합니다.

입력에는 자기 Bias 회로가 내장되어있지 않습니다.

Passive한 외부 Bias는 가능할 수 있습니다만,  Performance의 저하, 특히 THD+N이 원인이 됩니다.

차동 입력 ADC 제품에서 외부로부터 AINxN  pin은 무입력으로 AINxP pin에만 신호를 입력하면 어떤 현상이 발생힙니까?

[Q0059]

Answer

Device를 적절하게 동작시키기 위해서는 차동입력 AINxP pin에 신호를 입력하고, 그것과는 역상의 신호를 AINxN pin에 입력이 필요합니다.

차동 Pair의 입력 신호를 한쪽 만 구동하면 Level이 6dBFS로 저하하여 왜곡 특성의 열화가 발생합니다.

Datasheet에서 Power On/Off Sequence 중에 Idle Noise라는 것이 있는데 이것은 어떤 Noise입니까?

[Q0060]

Answer

Idle Noise라는 것은 통상 ADC 동작에 있어서의 무입력시의 Digital 출력입니다. S/N로 Spec화 하고있는 출력 Level입니다.

Power Down 상태에서 Register Access 는 가능합니까?

[Q0061]

Answer

Power Down 상태(PDN=low)에서 Register Access는 할 수 없습니다. Power Down 해제 후 Access 가능합니다.

그러나 일부의 Device에서는 Audio Clock이 없을 때는 Register에 Access 할 수 없는 것도 있습니다.

자세한 내용은 개별 Device의 Datasheet를 참조 하십시오.

FAQ - Audio ADCs

Audio A/D Converters

[Q0041]
・What are the clock input pin and the data output pin statuses in power-down mode?
A.
・The clock input pins are in Hi-z status. The data output pins are in Low level.
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[Q0042]
・Is there any restriction about PDN rising time?
A.
・There is no restriction about PDN rising time.
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[Q0043]
・Which action does execute power-down release: PDN pin level (H/L) detection or clcok edge input?
A.
・Power-down is released by MCLK and LRCK edges after the PDN pin is set to "H."
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[Q0044]
・What is the power-down sequence?
A.
・Stopping the clocks after setting the PDN pin = "H" → "L" is preferred. However, if the audio clocks are stopped first the device will enter power-down mode automatically for almost all recent generation devices. Please refer to the datasheet of each device in detail.
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[Q0045]
・Is there any problem if the PDN pin is kept to "L" when power supplies are On and then it is set to "H"? 
In the datasheet, it could be understood as that the PDN pin should be set to "L" first and set to "H" (H→L→H) after power supplies are on.
A.
・No Problem. Turn power supplies on while the PDN pin = "L" and then set the PDN pin to "H" after Reset period (tPD) is passed.
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[Q0046]
・When is the appropriate timing to input external clocks?
A.
・If the power supplies are On, external clocks can be input at any timing regardless of power-down release.
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[Q0047]
・Do I have to care about the input order of clocks?
A.
・There is no restriction about the input order of clocks.
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[Q0048]
・What does the expression "The LRCK clock input must be synchronized with MCLK, however the phase is not critical." in the datasheet mean substantially?
A.
・MCLK and LRCK should be generated by dividing the same clock source. The phase difference will not matter in this case.
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[Q0049]
・Is there any restriction about the rise/fall time of external input clock?
A.
・There is no timing restriction about the external clock input. However, the input clock swing must transit monotonically without including higher frequency noise.
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[Q0050]
・Does clock jitter on LRCK or BICK affect sound quality as well as clock jitter on MCLK?
A.
・The internal delta-sigma modulator operates on MCLK. LRCK and BICK are only used for latching input/output data, therefore generally clock jitter on LRCK or BICK does not affect the sound quality.
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[Q0051]
・How should the unused analog input pins be handled?
A.
・Handling may differ depending upon the specific ADC device. Single-ended input devices should normally be left open to allow the pin(s) to stabilize at their self-biasing point.
 Differential input devices should have their input+ and input- pins shorted together and the pair either grounded or left floating.
Each device should have specific recommendations in their respective datasheet Handling of Unused Pins section.
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[Q0052]
・How much capacitance does the digital input pin have?
A.
・The input capacitance will be less than 5pF.
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[Q0053]
・Does the digital input pin have internal pull up/down resistor?
A.
・The handling varies case-by-case of specific pins and specific devices. It will be specified in the datasheet if they have internal pull up/down resistors.
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[Q0054]
・DC offset is added to the AD output. What is it caused by?
A.
・Residual DC offset does occur by the conversion process and shall be evident if the digital HPF is disabled. In most cases enabling the HPF is a very satisfactory solution to eliminating this offset.
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[Q0055]
・Do you have a circuit diagram example of external analog input buffer circuit for channel summation mode?
A.
・Please refer to  the example of circuit diagram.
Click here for details
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[Q0056]
・Explain the Input Voltage specs (differential input device). For example, how are the units +/-2.8Vpp to be interpreted?
A.
・The meaning of +/-2.8Vpp spec units is the AINxP pin (plus input of any channel's differential input pair) is to swing its AC signal voltage portion at the level of 2.8Vpp, while the AINxN pin is to swing opposite phase and stated as -2.8Vpp. It is actually most conventionally correct to state this voltage as AINxP - AINxN = 5.6Vpp total swing of the differential pair. Notice that however stated this is only the AC portion of the signal swing relative to driving the ADC to full-scale and the voltage values are not referenced to ground. 
It is assumed that the proper signal conditions are to include the DC bias voltage of approx. VCOM = ~ (AVDD/2) which is to be also provided by the external buffer circuit.
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[Q0057]
・Explain the Input Voltage specs (single-ended input device). For example, how are the units 2.8Vpp to be interpreted?
A.
・The meaning of 2.8Vpp units the AINx pin (input of any channel) is to swing its AC signal voltage portion at the level of 2.8Vpp. Notice that this is only the AC portion of the signal swing relative to driving the ADC to full-scale and the voltage value is not referenced to ground. It is assumed that the proper signal conditions are to include the DC bias voltage of approx. VCOM = ~ (AVDD/2) which shall be provided internally by the self-biasing circuit while the signal is coupled via capacitor.
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[Q0058]
・Can I AC couple the input signal (differential input device)?
A.
・Generally, no, except the AK5730, AK5522 or AK5703 devices. High performance differential input devices require critical matching of the driving Op-amp circuit to the input's internal Sample and Hold circuit. The inputs do not contain any integrated self-biasing circuitry. Passive external biasing, while maybe possible, is likely to cause degraded performance, particularly THD+N.
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[Q0059]
・Can I drive only the AINxP input signal single-ended, while not driving AINxN (differential input device)?
A.
・Normal swing of both the AINxP input while the AINxN input is driven with opposite phase is necessary to properly drive the device to full-scale. Driving only one input signal of the differential pair will result in only -6dBFS level until abnormal distortion will occur as the level is attempted to be increased.
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[Q0060]
・What kind of noise is Idle Noise? It is written in the power on/off sequence of the datasheet for ADC.
A.
・Idle Noise is a digital output without input signal in normal ADC operation. It is the same output as the S/N specification.
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[Q0061]
・Is a register access valid in power-down mode?
A.
・Register access is not valid if PDN is LOW. However, certain devices do allow register access while the audio clocks are stopped and the device is in power-down mode automatically. Conditions for when register access is not allowed specific to each device are specified in notes at the bottom of the first page of the Register Control Interface section in the datasheet.
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