FAQ

Audio A/D Converters

Audio A/D Converters

[Q0041]
・What are the clock input pin and the data output pin statuses in power-down mode?
A.
・The clock input pins are in Hi-z status. The data output pins are in Low level.
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[Q0042]
・Is there any restriction about PDN rising time?
A.
・There is no restriction about PDN rising time.
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[Q0043]
・Which action does execute power-down release: PDN pin level (H/L) detection or clcok edge input?
A.
・Power-down is released by MCLK and LRCK edges after the PDN pin is set to "H."
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[Q0044]
・What is the power-down sequence?
A.
・Stopping the clocks after setting the PDN pin = "H" → "L" is preferred. However, if the audio clocks are stopped first the device will enter power-down mode automatically for almost all recent generation devices. Please refer to the datasheet of each device in detail.
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[Q0045]
・Is there any problem if the PDN pin is kept to "L" when power supplies are On and then it is set to "H"? 
In the datasheet, it could be understood as that the PDN pin should be set to "L" first and set to "H" (H→L→H) after power supplies are on.
A.
・No Problem. Turn power supplies on while the PDN pin = "L" and then set the PDN pin to "H" after Reset period (tPD) is passed.
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[Q0046]
・When is the appropriate timing to input external clocks?
A.
・If the power supplies are On, external clocks can be input at any timing regardless of power-down release.
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[Q0047]
・Do I have to care about the input order of clocks?
A.
・There is no restriction about the input order of clocks.
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[Q0048]
・What does the expression "The LRCK clock input must be synchronized with MCLK, however the phase is not critical." in the datasheet mean substantially?
A.
・MCLK and LRCK should be generated by dividing the same clock source. The phase difference will not matter in this case.
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[Q0049]
・Is there any restriction about the rise/fall time of external input clock?
A.
・There is no timing restriction about the external clock input. However, the input clock swing must transit monotonically without including higher frequency noise.
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[Q0050]
・Does clock jitter on LRCK or BICK affect sound quality as well as clock jitter on MCLK?
A.
・The internal delta-sigma modulator operates on MCLK. LRCK and BICK are only used for latching input/output data, therefore generally clock jitter on LRCK or BICK does not affect the sound quality.
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[Q0051]
・How should the unused analog input pins be handled?
A.
・Handling may differ depending upon the specific ADC device. Single-ended input devices should normally be left open to allow the pin(s) to stabilize at their self-biasing point.
 Differential input devices should have their input+ and input- pins shorted together and the pair either grounded or left floating.
Each device should have specific recommendations in their respective datasheet Handling of Unused Pins section.
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[Q0052]
・How much capacitance does the digital input pin have?
A.
・The input capacitance will be less than 5pF.
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[Q0053]
・Does the digital input pin have internal pull up/down resistor?
A.
・The handling varies case-by-case of specific pins and specific devices. It will be specified in the datasheet if they have internal pull up/down resistors.
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[Q0054]
・DC offset is added to the AD output. What is it caused by?
A.
・Residual DC offset does occur by the conversion process and shall be evident if the digital HPF is disabled. In most cases enabling the HPF is a very satisfactory solution to eliminating this offset.
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[Q0055]
・Do you have a circuit diagram example of external analog input buffer circuit for channel summation mode?
A.
・Please refer to  the example of circuit diagram.
Click here for details
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[Q0056]
・Explain the Input Voltage specs (differential input device). For example, how are the units +/-2.8Vpp to be interpreted?
A.
・The meaning of +/-2.8Vpp spec units is the AINxP pin (plus input of any channel's differential input pair) is to swing its AC signal voltage portion at the level of 2.8Vpp, while the AINxN pin is to swing opposite phase and stated as -2.8Vpp. It is actually most conventionally correct to state this voltage as AINxP - AINxN = 5.6Vpp total swing of the differential pair. Notice that however stated this is only the AC portion of the signal swing relative to driving the ADC to full-scale and the voltage values are not referenced to ground. 
It is assumed that the proper signal conditions are to include the DC bias voltage of approx. VCOM = ~ (AVDD/2) which is to be also provided by the external buffer circuit.
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[Q0057]
・Explain the Input Voltage specs (single-ended input device). For example, how are the units 2.8Vpp to be interpreted?
A.
・The meaning of 2.8Vpp units the AINx pin (input of any channel) is to swing its AC signal voltage portion at the level of 2.8Vpp. Notice that this is only the AC portion of the signal swing relative to driving the ADC to full-scale and the voltage value is not referenced to ground. It is assumed that the proper signal conditions are to include the DC bias voltage of approx. VCOM = ~ (AVDD/2) which shall be provided internally by the self-biasing circuit while the signal is coupled via capacitor.
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[Q0058]
・Can I AC couple the input signal (differential input device)?
A.
・Generally, no, except the AK5730, AK5522 or AK5703 devices. High performance differential input devices require critical matching of the driving Op-amp circuit to the input's internal Sample and Hold circuit. The inputs do not contain any integrated self-biasing circuitry. Passive external biasing, while maybe possible, is likely to cause degraded performance, particularly THD+N.
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[Q0059]
・Can I drive only the AINxP input signal single-ended, while not driving AINxN (differential input device)?
A.
・Normal swing of both the AINxP input while the AINxN input is driven with opposite phase is necessary to properly drive the device to full-scale. Driving only one input signal of the differential pair will result in only -6dBFS level until abnormal distortion will occur as the level is attempted to be increased.
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[Q0060]
・What kind of noise is Idle Noise? It is written in the power on/off sequence of the datasheet for ADC.
A.
・Idle Noise is a digital output without input signal in normal ADC operation. It is the same output as the S/N specification.
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[Q0061]
・Is a register access valid in power-down mode?
A.
・Register access is not valid if PDN is LOW. However, certain devices do allow register access while the audio clocks are stopped and the device is in power-down mode automatically. Conditions for when register access is not allowed specific to each device are specified in notes at the bottom of the first page of the Register Control Interface section in the datasheet.
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